Visible to Intel only — GUID: vgo1395820527630
Ixiasoft
Visible to Intel only — GUID: vgo1395820527630
Ixiasoft
2.3. UFM Block Diagrams
This figure shows the top level view of the On-Chip Flash Intel® FPGA IP core block diagram. The On-Chip Flash Intel® FPGA IP core supports both parallel and serial interfaces for Intel® MAX® 10 FPGAs.
- Data—a wrapper of the UFM block that provides read and program accesses to the flash.
- Control—the CSR and status register for the flash, which is required only for program and erase operations.
These figures show the detailed overview of the Avalon-MM interface during read and program (write) operation.
These figures show the detailed overview of the Avalon-MM interface during read only operation.
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