Intel® MAX® 10 User Flash Memory User Guide

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ID 683180
Date 8/30/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 User Flash Memory Overview 2. Intel® MAX® 10 UFM Architecture and Features 3. Intel® MAX® 10 UFM Design Considerations 4. Intel® MAX® 10 UFM Implementation Guides 5. On-Chip Flash Intel® FPGA IP Core References 6. Intel® MAX® 10 User Flash Memory User Guide Archive 7. Document Revision History for the Intel® MAX® 10 User Flash Memory User Guide
2. Intel® MAX® 10 UFM Architecture and Features x
2.1. UFM and CFM Array Size 2.2. UFM Memory Organization Map 2.3. UFM Block Diagrams 2.4. UFM Operating Modes
3. Intel® MAX® 10 UFM Design Considerations x
3.1. Guideline: UFM Power Supply Requirement 3.2. Guideline: Program and Read UFM with JTAG 3.3. Guideline: UFM Content Initialization 3.4. Guideline: Erase Before Program
4. Intel® MAX® 10 UFM Implementation Guides x
4.1. On-Chip Flash Intel® FPGA IP Core 4.2. UFM Avalon-MM Operating Modes 4.3. Flash Initialization Files
4.2. UFM Avalon-MM Operating Modes x
4.2.1. UFM Read Status and Control Register 4.2.2. UFM Write Control Register 4.2.3. UFM Program (Write) Operation 4.2.4. UFM Sector Erase Operation 4.2.5. UFM Page Erase Operation 4.2.6. UFM Read Operation 4.2.7. UFM Burst Read Operation
4.2.7. UFM Burst Read Operation x
4.2.7.1. UFM Data Incrementing Burst Read 4.2.7.2. UFM Data Wrapping Burst Read
5. On-Chip Flash Intel® FPGA IP Core References x
5.1. On-Chip Flash Intel® FPGA IP Core Parameters 5.2. On-Chip Flash Intel® FPGA IP Core Signals 5.3. On-Chip Flash Intel® FPGA IP Core Registers
5.3. On-Chip Flash Intel® FPGA IP Core Registers x
5.3.1. Sector Address
1. Intel® MAX® 10 User Flash Memory Overview
2. Intel® MAX® 10 UFM Architecture and Features
3. Intel® MAX® 10 UFM Design Considerations
4. Intel® MAX® 10 UFM Implementation Guides
5. On-Chip Flash Intel® FPGA IP Core References
6. Intel® MAX® 10 User Flash Memory User Guide Archive
7. Document Revision History for the Intel® MAX® 10 User Flash Memory User Guide

2.3. UFM Block Diagrams

This figure shows the top level view of the On-Chip Flash Intel® FPGA IP core block diagram. The On-Chip Flash Intel® FPGA IP core supports both parallel and serial interfaces for Intel® MAX® 10 FPGAs.

Figure 1. On-Chip Flash Intel® FPGA IP Core Block Diagram
This IP block has two Avalon-MM slave controllers:
  • Data—a wrapper of the UFM block that provides read and program accesses to the flash.
  • Control—the CSR and status register for the flash, which is required only for program and erase operations.

These figures show the detailed overview of the Avalon-MM interface during read and program (write) operation.

Figure 2. On-Chip Flash Intel® FPGA IP Core Avalon-MM Slave Read and Program (Write) Operation in Parallel ModeThis figure shows the standard interface for Intel® MAX® 10 devices in parallel mode.
Note: The maximum frequency for all devices in parallel mode, except for 10M02 2, is 116 MHz. The maximum frequency for 10M022 devices is 7.25 MHz.
Figure 3. On-Chip Flash Intel® FPGA IP Core Avalon-MM Slave Read and Program (Write) Operation in Serial ModeThis figure shows the standard interface for Intel® MAX® 10 devices in serial mode.

These figures show the detailed overview of the Avalon-MM interface during read only operation.

Figure 4. On-Chip Flash Intel® FPGA IP Core Avalon-MM Slave Read Only Operation in Parallel Mode
Figure 5. On-Chip Flash Intel® FPGA IP Core Avalon-MM Slave Read Only Operation in Serial Mode
2 10M02 does not include 10M02SCU324.
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