Intel® Accelerator Functional Unit (AFU) Simulation Environment (ASE) Quick Start User Guide

ID 683159
Date 4/11/2018
Public

1.6. Simulating your Custom AFU

Standard Simulation Scripts

To simulate your custom AFU, Intel recommends that you copy an existing AFU from the release package and modify it as necessary.
Figure 7. Sample Directory Structure for Standard Simulation Scripts
ASE automatically scans and includes RTL source files under <afu_name>/hw/rtl during simulation.

Custom Simulation Scripts

Custom simulation scripts can be placed under <afu_name>/hw/sim. You need custom simulation scripts if you don’t want ASE to include every RTL source file placed under <afu_name>/hw/rtl. You may need custom simulation scripts if your AFU includes Platform Designer systems.
Figure 8. Sample Directory Structure for Custom Simulation Scripts

Intel recommends you to follow $OPAE_LOC/samples/dma_afu if you want to use custom simulation scripts.

Intel recommends to run the simulation using either setup_sim.sh, run_app.sh or regress.sh under $DCP_LOC/hw/common/scripts. If your AFU uses a custom simulation script, the standard simulation script will automatically find and invoke it. The custom simulation scripts must reside at <path to afu>/hw/sim, if you want the standard simulation script to automatically find and invoke them.

The sim_common.sh under $DCP_LOC/hw/common/scripts provides a handy collection of bash functions for ASE setup. For more information about ASE scripts, refer to Intel® Accelerator Functional Unit (AFU) Simulation Environment (ASE) User Guide. If the AFU consists of one or more Platform Designer systems, use the simulation scripts available under dma_afu as a reference.

If you choose to write custom simulation scripts instead of using the bash routines in sim_common.sh, you must ensure to define the following text macros for the simulation to work properly:
+define+INCLUDE_DDR4
+define+DDR_ADDR_WIDTH=26
You can add these text macros in the ase_sources.mk file.
Example (VCS):
echo "SNPS_VLOGAN_OPT+= +define+INCLUDE_DDR4 +define+DDR_ADDR_WIDTH=26" >> ase_sources.mk

Example(Modelsim/Questa)
echo "MENT_VLOG_OPT += +define+INCLUDE_DDR4 +define+DDR_ADDR_WIDTH=26" >> ase_sources.mk
For Modelsim/Questa, you must suppress the following error message codes:
  • 3485
  • 3584
Add the error codes to suppress ase_sources.mk file using the following:
echo "MENT_VLOG_OPT += -suppress 3485,3584" >> ase_sources.mk
echo "MENT_VSIM_OPT += -suppress 3485,3584" >> ase_sources.mk
Note: The ASE memory model supports configurable address width for FPGA local memory. Supported address widths are 26 bits (8G) and 27 bits (16G). Default configuration is 26 bits (8G). You can customize the address width using the parameter DDR_ADDR_WIDTH.
For example:
  • To configure the ASE memory model to 16G configuration in VCS:
    echo "SNPS_VLOGAN_OPT +define+DDR_ADDR_WIDTH=27" >> ase_sources.mk
  • To configure the ASE memory model to 16G configuration in Modelsim/Questa:
    echo "MENT_VLOG_OPT += +define+DDR_ADDR_WIDTH=27" >> ase_sources.mk

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