1. Intel® Accelerator Functional Unit (AFU) Simulation Environment (ASE)
|Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.0 Production|
The ASE provides a transactional model for the Core Cache Interface (CCI-P) protocol and a memory model for the FPGA-attached local memory. The CCI-P transactional model verifies CCI-P protocol correctness. The local memory model provides a simulation model for the dual-memory banks on the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs daughtercard.
The ASE also validates Accelerator Functional Unit (AFU) compliance to the following protocols and APIs:
- CCI-P protocol specification
- Avalon® Memory Mapped ( Avalon® -MM) Interface Specification
- Open Programmable Acceleration Engine
This document describes how to simulate a sample AFU using the ASE environment. Refer to Intel® Accelerator Functional Unit (AFU) Simulation Environment (ASE) User Guide for comprehensive details on ASE capabilities and internal architecture.
|Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs||Acceleration Stack||
A collection of software, firmware and tools that provides performance-optimized connectivity between an Intel® FPGA and an Intel® Xeon® processor.
|Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA||Intel® PAC with Arria® 10 GX FPGA||
PCIe* accelerator card with an Intel® Arria® 10 FPGA.
Contains a FPGA Interface Manager (FIM) that pairs with an Intel® Xeon® processor over PCIe* bus.
|Intel® Xeon® Scalable Platform with Integrated FPGA||Integrated FPGA Platform||
Intel® Xeon® plus FPGA platform with the Intel® Xeon® and an FPGA in a single package and sharing a coherent view of memory via Ultra Path Interconnect (UPI).
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