Intel® Accelerator Functional Unit (AFU) Simulation Environment (ASE) Quick Start User Guide

ID 683159
Date 4/11/2018

1.5. Simulating the hello_afu AFU using the ASE (Regression Mode)

Use the script, located in $DCP_LOC/hw/common/scripts, to execute the simulator and the application exactly once.

  1. $ cd $DCP_LOC/hw/common/scripts
  2. Usage: -a <afu dir> -s <vcs|modelsim|questa> -b <opae base dir> [-i <opae install path>] [-r <rtl simulation dir>] [-m <EMIF_MODEL_BASIC|EMIF_MODEL_ADVANCED> memory model]
    Table 4.  Flag Descriptions
    Flag Description Legal Values Default Required
    -a Path to AFU source

    Example: $DCP_LOC/hw/samples/hello_afu - Yes
    -s Simulator type vcs, modelsim, questa - Yes
    -b $OPAE_LOC $OPAE_LOC - Yes
    -r Optional directory to build the simulation.

    If specified, AFU source and ASE work directory is copied here. If not, simulation is built in OPAE_LOC/rtl_sim

    - $OPAE_LOC/rtl_sim No
    -m Local Memory Model: selects the simulation model for FPGA private memory. Supported values are EMIF_MODEL_BASIC and EMIF_MODEL_ADVANCED.

    EMIF_MODEL_BASIC uses a simple system-verilog array to model dual banks of DRAM.

    EMIF_MODEL_ADVANCED uses an advanced cycle accurate model of the EMIF memory controller.

    EMIF_MODEL_BASIC is recommended for faster simulations.

    -i Optional path to OPAE installation2. You must specify the install path if you don’t use the RPM flow. If you are using the RPM flow, the install path is not required. <custom opae_loc directory>

    Example: /home/john/opaeinstall

    - No
Follow these steps from both Client-Server and Regression mode to simulate other AFUs listed below:
Table 5.  AFU Examples
AFU Description
nlb_mode_0 nlb_mode_0 demonstrates the memory copy test. The software application is located at $DCP_LOC/sw/opae-<release_number>/sample/hello_fpga.c
hello_intr_afu hello_intr_afu demonstrates the user interrupt feature in ASE.
dma_afu (only Client-Server mode) dma_afu demonstrates a DMA Basic Building Block for host to FPGA, FPGA to host and FPGA to FPGA memory transfers. When simulating this AFU, the buffer size used for DMA transfer is intentionally kept small to keep the simulation time reasonable.
2 If you built OPAE from the source instructed in Building the OPAE Software section of Intel Acceleration Stack Quick Start Guide for , provide the installation path. For example:/home/john/opaeinstall

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