Guidelines for Developing a Nios II HAL Device Driver

ID 683146
Date 6/12/2015
Public
Document Table of Contents

1. Guidelines for Developing a Nios II HAL Device Driver

This application note explains the process of creating and debugging a hardware abstraction layer (HAL) software device driver. The included example of a HAL software device driver, called my_uart_driver, illustrates various software development stages. The example driver targets the Altera_Avalon_UART device, connected through a Vectored Interrupt Controller (VIC) to the Nios® II processor.

This application note helps you with custom device driver development for Nios II systems in the following ways:

  • Shows the development process steps, from sending bits out the transmit pin in the main() through the construction of device access macros and automatic device initialization in alt_sys_init()
  • Shows how to develop a driver with the command-line based Nios II Software Build Tools (SBT)
  • Shows how to create applications and a board support package (BSP) based on your driver
  • Shows how to import and debug the applications and BSP with the Nios II Software Build Tools for Eclipse
  • Explains interrupt latency, interrupt nesting, and determinism
  • Identifies system calls that cannot be included in a device driver interrupt service routine (ISR)
  • Describes debugging tips and techniques, such as identifying UART transmission errors
Note: This application note uses the Nios II Gen2, Cyclone® V E FPGA Development Kit, as an example hardware platform.

For more information about the HAL, refer to the "Overview of the Hardware Abstraction Layer" chapter in the Nios II Software Developer's Handbook. For more information about interrupt latency, refer to the "Exception Handling" chapter in the Nios II Software Developer's Handbook.

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