126.96.36.199. Specify Instance-Specific Constraints in Assignment Editor 188.8.131.52. Specify NoC Constraints in NoC Assignment Editor 184.108.40.206. Specify I/O Constraints in Pin Planner 220.127.116.11. Plan Interface Constraints in Interface Planner and Tile Interface Planner 18.104.22.168. Adjust Constraints with the Chip Planner 22.214.171.124. Constraining Designs with the Design Partition Planner
3.2.1. Assigning to Exclusive Pin Groups 3.2.2. Assigning Slew Rate and Drive Strength 3.2.3. Assigning I/O Banks 3.2.4. Changing Pin Planner Highlight Colors 3.2.5. Showing I/O Lanes 3.2.6. Assigning Differential Pins 3.2.7. Entering Pin Assignments with Tcl Commands 3.2.8. Entering Pin Assignments in HDL Code
126.96.36.199. Step 3: Update Plan with Project Assignments
You can determine which fixed assignments to load from the project settings .qsf, and optionally load the latest placement from Logic Generation. The enabled assignments become the starting point for the tile plan. Follow these steps to update the plan with existing assignments:
- On the Flow control, click View Assignments.
Figure 34. Plan Assignment Options
- On the Assignments tab, select the assignment types to load for the current planning session, as Assignments Tab Controls describes.
- On the Assignments tab, enable or disable assignments to resolve any conflicts or experiment with alternative placements. Filter the list of assignments by assignment name or status.
Figure 35. Enable or Disable Existing Assignments for Current Planning Session
- When assignment selections are complete, or if you have no existing assignments, click Update Plan on the Flow control to apply the enabled project assignments to your current tile interface plan.
- Place IP components and building blocks on the Plan tab, as Step 4: Create a Tile Plan describes.