184.108.40.206. Specify Instance-Specific Constraints in Assignment Editor 220.127.116.11. Specify NoC Constraints in NoC Assignment Editor 18.104.22.168. Specify I/O Constraints in Pin Planner 22.214.171.124. Plan Interface Constraints in Interface Planner and Tile Interface Planner 126.96.36.199. Adjust Constraints with the Chip Planner 188.8.131.52. Constraining Designs with the Design Partition Planner
3.2.1. Assigning to Exclusive Pin Groups 3.2.2. Assigning Slew Rate and Drive Strength 3.2.3. Assigning I/O Banks 3.2.4. Changing Pin Planner Highlight Colors 3.2.5. Showing I/O Lanes 3.2.6. Assigning Differential Pins 3.2.7. Entering Pin Assignments with Tcl Commands 3.2.8. Entering Pin Assignments in HDL Code
184.108.40.206. Step 2: Initialize Tile Interface Planner
When you launch Tile Interface Planner, the tool initializes the placement legality engine and loads component IP and target device data extracted by Design Analysis. Tile Interface Planner then displays the component IP information in the Design Tree view and enables the Flow control.
Tile Interface Planner Flow Control
To initialize Tile Interface Planner:
- Run the Design Analysis stage of the Compiler, as Step 1: Instantiate IP and Run Design Analysis describes.
- When Design Analysis is complete, launch Tile Interface Planner by clicking the Tile Interface Planner icon in the Compilation Dashboard, the main toolbar, or by clicking Tools > Tile Interface Planner.
Figure 33. Launching Tile Interface Planner
Tile Interface Planner launches and initializes with the legality engine and the component IP and target device data that Design Analysis extracts.
- Load existing project assignments, as Step 3: Update Plan with Project Assignments describes.