126.96.36.199. Specify Instance-Specific Constraints in Assignment Editor 188.8.131.52. Specify NoC Constraints in NoC Assignment Editor 184.108.40.206. Specify I/O Constraints in Pin Planner 220.127.116.11. Plan Interface Constraints in Interface Planner and Tile Interface Planner 18.104.22.168. Adjust Constraints with the Chip Planner 22.214.171.124. Constraining Designs with the Design Partition Planner
3.2.1. Assigning to Exclusive Pin Groups 3.2.2. Assigning Slew Rate and Drive Strength 3.2.3. Assigning I/O Banks 3.2.4. Changing Pin Planner Highlight Colors 3.2.5. Showing I/O Lanes 3.2.6. Assigning Differential Pins 3.2.7. Entering Pin Assignments with Tcl Commands 3.2.8. Entering Pin Assignments in HDL Code
126.96.36.199.1. Design Tree and Filters
The Design Tree View displays a hierarchy of the IP components and building block design elements found during the Design Analysis compilation stage. You can locate the IP and building blocks in the design tree, and then assign the elements to legal locations in the tile floorplan on the Plan tab.
The Design Tree view includes these columns:
- Design Element—lists all component IP and building blocks that Design Analysis identifies. IP cores and building blocks are distinguished by different icons. Fixed IP building blocks are shown in plain text. Movable IP building blocks are shown in italic text. Always movable building blocks are shown in gray italic text.
- Highlight—indicates the color for display of design elements in the tile visualization pane.
- Placement—indicates the placement status (placed, unplaced) or placement tile location for design elements.
You can type a partial or complete name in the design element filter field to refine the list of elements displayed.
- Click the Full icon to show all design elements in the tree.
- Click the IP icon to show only IP level hierarchy in the tree.
- Click the Unplaced icon to show only unplaced design elements in the tree.
- Click the I/Os icon to show only I/O design elements in the tree.