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1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor
1.1.2.2. Specify NoC Constraints in NoC Assignment Editor
1.1.2.3. Specify I/O Constraints in Pin Planner
1.1.2.4. Plan Interface Constraints in Interface Planner and Tile Interface Planner
1.1.2.5. Adjust Constraints with the Chip Planner
1.1.2.6. Constraining Designs with the Design Partition Planner
3.2.1. Assigning to Exclusive Pin Groups
3.2.2. Assigning Slew Rate and Drive Strength
3.2.3. Assigning I/O Banks
3.2.4. Changing Pin Planner Highlight Colors
3.2.5. Showing I/O Lanes
3.2.6. Assigning Differential Pins
3.2.7. Entering Pin Assignments with Tcl Commands
3.2.8. Entering Pin Assignments in HDL Code
Visible to Intel only — GUID: mwh1410470993702
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1.1.2. Node, Entity, and Instance-Level Constraints
Node, entity, and instance-level constraints apply to a subset of the design hierarchy. These constraints take precedence over any global assignment that affects the same sections of the design hierarchy. The following tools are available in the Intel® Quartus® Prime software to specify node, entity, and instance-level constraints:
Assignment Type | Assignment Editor | Interface Planner | NoC Assignment Editor | Chip Planner | Pin Planner |
---|---|---|---|---|---|
Pin | X | X | |||
Location | X | X | X | ||
Routing | X | X | |||
NoC | X | ||||
Simulation | X | X | X |
Although you can specify constraints using a variety of tools, the following table shows the most effective constraint tools at each design phase:
Design Phase | Assignment Editor | NoC Assignment Editor | Interface Planner | Tile Interface Planner | Chip Planner | Timing Analyzer | Pin Planner |
---|---|---|---|---|---|---|---|
Pre-Synthesis | X | X | X | X | |||
Post-Synthesis | X | X | X | X | |||
Post-Fit | X | X | X | X |
Section Content
Specify Instance-Specific Constraints in Assignment Editor
Specify NoC Constraints in NoC Assignment Editor
Specify I/O Constraints in Pin Planner
Plan Interface Constraints in Interface Planner and Tile Interface Planner
Adjust Constraints with the Chip Planner
Constraining Designs with the Design Partition Planner