Intel® Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 12/04/2023
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2.1.3.1.1. Recommended Placement Order for NoC Elements in Interface Planner

For best results, place NoC-related elements in the following order:

Note: For important considerations when choosing initiator interface placement, refer to Horizontal Bandwidth Considerations in the Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide to translate location choices into physical placements.
  1. Start by placing the NoC PLL and SSM in the Interface Planner Chip View. Expand the contents of the NoC Clock Control IP by clicking the small triangle to the left of the IP instance name (noc_clock_ctrl_0) in the Design Element pane. Place the PLL and SSM instances for each clock control IP at either the top corner or the bottom corner.
  2. Use the Autoplace Selected command to place the remaining NoC Clock Control Intel FPGA IP.
  3. If using HBM2e memory, start by placing the UIB PLL using the Interface Planner Chip View. Expand the contents of the HBM2e IP by clicking the small triangle to the left of the IP instance name (hbm_fp_0) in the Design Element pane. Interface Planner may display legal locations on both the top edge and on the bottom edge of the die. Place the IP along the same edge of the die as the corresponding NoC PLL.
  4. Place the HBM2e instance (design element name ending in …|xhbmc). Interface Planner displays only one legal location for the HBM2e instance.
  5. Use Autoplace Selected to place the remaining HBM2e IP, including all NoC target interfaces.
  6. If using high-speed external memory interfaces that connect to the NoC, place these interfaces next. As with the HBM2e Intel FPGA IP above, start by placing the PLL for the external memory interface. Ensure you place this interface along the same edge as the corresponding NoC PLL.
  7. Place the mem_ck pins to fix the pin-out for the interface.
  8. Use Autoplace Selected to place the remaining external memory interface IP, including all of the NoC target interfaces.
  9. Select the NoC View to place the initiator interfaces. The NoC View shows the target interfaces that you already placed. As you place each initiator, the targets you connect to highlight. When placing each initiator, consider which targets communicate with the initiator.

Low-speed external memory interfaces and other GPIO functions that bypass the NoC can conflict with initiator interface placement. Depending on design requirements, you can place these I/O functions that bypass the NoC before or after placing the NoC initiator interfaces. Placing I/O functions first gives greater flexibility to their placement, while restricting which initiator locations you can use. Placing NoC initiator interfaces first allows optimal initiator placement, while restricting which I/O locations are available.

Other interfaces, such as transceivers, have no direct interaction with the hard memory NoC. Therefore, you can place such interfaces before or after the NoC.