126.96.36.199. Specify Instance-Specific Constraints in Assignment Editor 188.8.131.52. Specifying Multi-Dimensional Bus Constraints 184.108.40.206. Specify I/O Constraints in Pin Planner 220.127.116.11. Plan Interface Constraints in Interface Planner and Tile Interface Planner 18.104.22.168. Adjust Constraints with the Chip Planner 22.214.171.124. Constraining Designs with the Design Partition Planner
126.96.36.199. Step 1: Instantiate IP and Run Design Analysis 188.8.131.52. Step 2: Initialize Tile Interface Planner 184.108.40.206. Step 3: Update Plan with Project Assignments 220.127.116.11. Step 4: Create a Tile Plan Recommended Two-Stage Tile IP Placement 18.104.22.168. Step 5: Save Tile Plan Assignments 22.214.171.124. Step 6: Run Logic Generation and Design Synthesis
126.96.36.199. Step 4: Create a Tile Plan
Click Plan Design on the Flow control to interactively place component IP in legal locations on device tiles. The Plan tab displays a hierarchical list of your project component IP design elements, alongside a graphical abstraction of the target device tile architecture. Place IP (and IP building blocks) in legal tile locations within the graphical tile floorplan.
Tile Interface Planner Design Elements and Chip View
Recommended Two-Stage Tile IP Placement
Handle IP tile placement in two stages for the most efficiency:
|Tile IP Placement||Description|
Note: Changes made in Tile Interface Planner do not apply to your Intel® Quartus® Prime project until you apply the generated tile interface plan constraints to your project, as Step 5: Save Tile Plan Assignments describes.
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