Intel® Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 10/04/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2. Interface Planning

Interface planning—the feasibility analysis of interface physical constraints—is a fundamental early step in advanced FPGA design. Periphery placement can be a complex process involving many variables. The Intel® Quartus® Prime Interface Planner simplifies the planning of accurate constraints for physical implementation.

You can use the Interface Planner to prototype interface implementations, plan clocks, and rapidly define a legal device floorplan.

Similarly, when targeting the Intel® Agilex™ F-tile devices, you can use the Tile Interface Planner build a plan for placement of IP components in each tile available on the FPGA device.

Interface Planner and Tile Interface Planner (launched from the Tools menu) interact dynamically with the Intel® Quartus® Prime Fitter to accurately verify placement legality while placing elements. You can evaluate different floorplans, using interactive reports to accurately plan the best implementation without iterative compilation. Fitter verification ensures the highest correlation between your interface plan or tile interface plan and actual implementation results. You can apply the interface plan or tile interface plan constraints to your project with high confidence in the final implementation.