Intel® Quartus® Prime Pro Edition User Guide: Design Constraints

ID 683143
Date 10/04/2021
Public

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2.2.2.4.3. Multi-Rate IP Tile Planning

Tile Interface Planner provides support for tile planning with multi-rate IP components, such as the F-tile CPRI PHY Multi-Rate Intel FPGA IP.

Tile Interface Planner displays the tile location of multi-rate IP and building blocks in your project. Tile Interface Planner shows the initial, read-only multi-rate IP profile as profile_0 in the Design Element hierarchy.

You cannot edit the multi-rate IP tile location in the current version of Tile Interface Planner. However, you can view the multi-rate IP tile location, and then place other IP components in relation to that location.

To perform tile planning with multi-rate IP, follow these steps:
  1. Instantiate and elaborate a multi-rate IP component in your design, as Step 1: Instantiate IP and Run Design Analysis describes.
    Note: Tile Interface Planner currently supports only the F-tile CPRI PHY Multi-Rate Intel FPGA IP for multi-rate tile planning.
  2. Start Tile Interface Planner, as Step 2: Initialize Tile Interface Planner describes.
  3. Update the plan with existing assignments, as Step 3: Update Plan with Project Assignments describes.
  4. In Tile Interface Planner, click the Plan tab. Tile Interface Planner displays the initial, read-only multi-rate IP profile as profile_0 in the Design Element hierarchy. The Placement column is grayed, indicating that the multi-rate IP placement is not editable in the current version of Tile Interface Planner.
    Figure 36. Multi-Rate IP in Tile Interface Planner
  5. Expand the multi-rate IP's "bb_" subfolders to view the multi-rate IP's building blocks for the initial dynamic reconfiguration profile.
    Figure 37. Multi-Rate IP Building Blocks for Initial Multi-Rate Profile
  6. Place other IP components in relation to that location, as Placing IP Components describes.
    Figure 38. Placing Other IP Components

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