AN 808: Migration Guidelines from Intel® Arria® 10 to Intel® Stratix® 10 for 10G Ethernet Subsystem

ID 683141
Date 11/20/2019
Public

Intel® Stratix® 10 LL 10GbE MAC and Intel® Stratix® 10 Transceiver Native PHY IP Cores

You can configure the Intel® Stratix® 10 Transceiver Native PHY IP core to implement 10GBASE-R PHY with the Ethernet-specific physical layer running at 10.3125 Gbps data rate as defined in Clause 49 of IEEE 802.3-2008 specification. This configuration provides an XGMII to LL 10GbE MAC Intel® FPGA IP core and implements a single-channel 10.3125Gbps PHY for a direct connection to a small form-factor pluggable plus (SFP+) optical module using the small form-factor interface (SFI) electrical specification.

The following figure illustrates the migration from an Intel® Arria® 10 design to a Intel® Stratix® 10 design.

Figure 2. Clocking and Reset Scheme for LL 10GbE MAC and Intel® Stratix® 10 Transceiver Native PHY in 10GBASE-R Design Example Interface

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