AN 808: Migration Guidelines from Intel® Arria® 10 to Intel® Stratix® 10 for 10G Ethernet Subsystem

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ID 683141
Date 11/20/2019
Public
Document Table of Contents
Document Table of Contents x
Migration Guidelines from Intel® Arria® 10 to Intel® Stratix® 10 for 10G Ethernet Subsystem
Migration Guidelines from Intel® Arria® 10 to Intel® Stratix® 10 for 10G Ethernet Subsystem x
Supported Configurations for Intel® Stratix® 10 and Intel® Arria® 10 LL 10GbE MAC Designs Clocking and Reset Infrastructure IP Register Mapping Signal Connectivity Differences between Intel® Stratix® 10 and Intel® Arria® 10 Ethernet Design Examples Migration Flow Document Revision History for AN 808: Migration Guidelines from Intel® Arria® 10 to Intel® Stratix® 10 for 10G Ethernet Subsystem
Clocking and Reset Infrastructure x
Intel® Stratix® 10 LL 10GbE MAC and Intel® Stratix® 10 Transceiver Native PHY IP Cores Intel® Stratix® 10 LL 10GbE MAC and Intel® Stratix® 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Cores
Migration Guidelines from Intel® Arria® 10 to Intel® Stratix® 10 for 10G Ethernet Subsystem

Document Revision History for AN 808: Migration Guidelines from Intel® Arria® 10 to Intel® Stratix® 10 for 10G Ethernet Subsystem

Document Version Changes
2019.11.20
  • Rebranded as Intel.
  • Updated Figure: Clocking and Reset Scheme for LL 10GbE MAC and 1G/2.5G/5G/10G Multi-rate Ethernet PHY Design Example (1G/2.5G Mode with IEEE 1588v2 Feature) for Intel® Stratix® 10 Devices.
  • Made editorial update throughout the document.
Date Version Changes
June 2017 2017.06.19 Initial release.
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