AN 808: Migration Guidelines from Intel® Arria® 10 to Intel® Stratix® 10 for 10G Ethernet Subsystem

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ID 683141
Date 11/20/2019
Public
Document Table of Contents
Document Table of Contents x
Migration Guidelines from Intel® Arria® 10 to Intel® Stratix® 10 for 10G Ethernet Subsystem
Migration Guidelines from Intel® Arria® 10 to Intel® Stratix® 10 for 10G Ethernet Subsystem x
Supported Configurations for Intel® Stratix® 10 and Intel® Arria® 10 LL 10GbE MAC Designs Clocking and Reset Infrastructure IP Register Mapping Signal Connectivity Differences between Intel® Stratix® 10 and Intel® Arria® 10 Ethernet Design Examples Migration Flow Document Revision History for AN 808: Migration Guidelines from Intel® Arria® 10 to Intel® Stratix® 10 for 10G Ethernet Subsystem
Clocking and Reset Infrastructure x
Intel® Stratix® 10 LL 10GbE MAC and Intel® Stratix® 10 Transceiver Native PHY IP Cores Intel® Stratix® 10 LL 10GbE MAC and Intel® Stratix® 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Cores
Migration Guidelines from Intel® Arria® 10 to Intel® Stratix® 10 for 10G Ethernet Subsystem

IP Register Mapping

The LL 10GbE MAC Intel® FPGA IP core for Intel® Stratix® 10 devices uses the same register map as LL 10GbE MAC Intel® FPGA IP core for Intel® Arria® 10 devices. The Multi-rate Ethernet PHY and 10GBASE-R PHY presets also use the same register map for both Intel® Stratix® 10 and Intel® Arria® 10 designs. The LL 10GbE MAC Intel® FPGA IP core for Intel® Stratix® 10 devices still supports backward compatibility with 10GbE IP with 64-bit Avalon Memory-Mapped (MM) adapter.

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