AN 808: Migration Guidelines from Intel® Arria® 10 to Intel® Stratix® 10 for 10G Ethernet Subsystem

ID 683141
Date 11/20/2019
Public

Intel® Stratix® 10 LL 10GbE MAC and Intel® Stratix® 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Cores

1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core for Intel® Stratix® 10 devices provides GMII and XGMII to the LL 10GbE MAC Intel® FPGA IP core. The 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP core implements a single channel 1G/2.5G/5G/10Gbps serial PHY. The design provides a direct connection to 1G/2.5GbE dual speed SFP+ pluggable modules, MGBASE-T copper external PHY devices, or chip-to-chip interfaces. These IP cores support reconfigurable data rates.

The following figure illustrates then migration from an Intel® Arria® 10 design to a Intel® Stratix® 10 design.

Figure 3. Clocking and Reset Scheme for LL 10GbE MAC and 1G/2.5G/5G/10G Multi-rate Ethernet PHY Design Example (1G/2.5G/10G Mode) for Intel® Stratix® 10 Deviecs

The following figure illustrates the latest clocking and reset scheme of the 1G/2.5G Ethernet with IEEE 1588v2 feature design example targeted on Intel® Stratix® 10 devices. There are differences between this solution and the version that was introduced in the Intel® Arria® 10 devices. Modification is needed when migrating design from the Intel® Arria® 10 devices to the Intel® Stratix® 10 devices.

Figure 4. Clocking and Reset Scheme for LL 10GbE MAC and 1G/2.5G/5G/10G Multi-rate Ethernet PHY Design Example (1G/2.5G Mode with IEEE 1588v2 Feature) for Intel® Stratix® 10 Devices

A new input clock port latency_sclk is available in Intel® Stratix® 10 devices. This port is available when you turn on the Enable latency measurement ports parameter in the Intel® Stratix® 10 L/H-Tile Transceiver Native PHY IP core or the Enable IEEE 1588 Precision Time Protocol parameter in the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core. This port is required for deterministic latency measurement model for Intel® Stratix® 10 devices. For more information, refer to the Deterministic Latency Use Model chapter in Intel® Stratix® 10 L/H-Tile Transceiver PHY User Guide.

To connect an I/O phase-locked loop (IOPLL), add a Intel® Stratix® 10 Clock Control (stratix10_clkctrl) IP from the IP Catalog. The IOPLL provides two sampling clocks in this design: 53.33 MHz for 2.5G mode and 80 MHz for 1G mode.

The following figure illustrates the connectivity details based on the 1G/2.5G Ethernet design.

Figure 5. Connectivity Diagram for 1G/2.5G Ethernet with 1588 Design for Intel® Stratix® 10 Devices

You must ensure that the inclk0x port connects to 2.5G sampling clock and the inclk1x port connects to 1G sampling clock. The output clock port of clock control becomes the latency_sclk port. For design migration from the Intel® Arria® 10 devices to the Intel® Stratix® 10 devices, you can reuse the similar connectivity between the 1G/2.5G reconfiguration block and transceiver reset controller.

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