AN 808: Migration Guidelines from Intel® Arria® 10 to Intel® Stratix® 10 for 10G Ethernet Subsystem

ID 683141
Date 11/20/2019
Public

Signal Connectivity Differences between Intel® Stratix® 10 and Intel® Arria® 10 Ethernet Design Examples

For LL 10GbE MAC Intel® FPGA IP core, there are no new signals introduced for Intel® Stratix® 10 devices. There are new asynchronous reset status signals introduced in Intel® Stratix® 10 L/H-Tile Transceiver Native PHY IP Core. The differences apply to all Ethernet PHY IP cores, which include all variants of 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP cores and 10GBASE-R PHY Intel® FPGA IP core.

Table 3.  Interface Signal Differences Between Intel® Stratix® 10 L/H-Tile Transceiver Native PHY/Multi-rate Ethernet PHY and Intel® Arria® 10 Transceiver Native PHY/Multi-rate Ethernet PHY
Note: <n> = The number of lanes.
Intel® Stratix® 10 Interface Signals Intel® Arria® 10 Interface Signals Comments
tx_analogreset_stat[<n>-1:0] Not available These reset status ports are newly introduced in Intel® Stratix® 10 devices only.

Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.

rx_analogreset_stat[<n>-1:0] Not available
tx_digitalreset_stat[<n>-1:0] Not available
rx_digitalreset_stat[<n>-1:0] Not available
latency_sclk Not available Latency measurement input reference clock. Sampling clock for measuring the latency of the transceiver application interface block (AIB) datapath.

This port is available when the latency measurement ports option in the Intel® Stratix® 10 L/H-Tile Transceiver Native PHY IP core or the IEEE 1588 Precision Time Protocol option in the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core is enabled.

reconfig_address [log2<n>+10:0] reconfig_address [log2<n>+9:0] Reconfiguration address signal connected to the reconfiguration block. Address bus that used to specify address to be accessed for both read and write operations.
Table 4.  Interface Signal Differences Between Intel® Stratix® 10 Transceiver Reset Controller IP and Intel® Arria® 10 Transceiver Reset Controller IP
Note: <n> = The number of lanes.
Intel® Stratix® 10 Interface Signals Intel® Arria® 10 Interface Signals Comments
tx_analogreset_stat[<n>-1:0] Not available This is reset status signal from the Transceiver Native PHY IP Core. There is one tx_analogreset_stat per channel.

When asserted, reset sequence for TX PMA begins.

When deasserted, reset sequence for TX PMA ends.

rx_analogreset_stat[<n>-1:0] Not available This is reset status signal from the Transceiver Native PHY IP Core. There is one rx_analogreset_stat per channel.

When asserted, reset sequence for RX PMA begins.

When deasserted, reset sequence for RX PMA ends.

tx_digitalreset_stat[<n>-1:0] Not available This is reset status signal from the Transceiver Native PHY IP Core. There is one tx_digitalreset_stat per channel.

When asserted, reset sequence for TX PCS begins.

When deasserted, reset sequence for TX PCS ends.

rx_digitalreset_stat[<n>-1:0] Not available This is reset status signal from the Transceiver Native PHY IP Core. There is one rx_digitalreset_stat per channel.

When asserted, reset sequence for RX PCS begins.

When deasserted, reset sequence for RX PCS ends.

The following figure illustrates the connectivity of reset status signals for the Intel® Stratix® 10 Ethernet 10G subsystem design. This is applicable if you use either the Intel® Stratix® 10 L-tile/H-tile Native PHY IP core or the 1G/2.5G/5G/10G Multi-rate PHY Intel® FPGA IP core.

Figure 6. Reset Status Signals Connectivity Diagram for Intel® Stratix® 10 PHY IP Core and Reset Controller IP Core

There are some changes to the ATX PLL and fPLL interface signals for the Intel® Stratix® 10 devices compared to the Intel® Arria® 10 devices. If you are migrating Ethernet designs from a Intel® Arria® 10 device to a Intel® Stratix® 10 device, remove the mcgb_rst and pll_powerdown reset signals because they are not available in Intel® Stratix® 10.

The following figure illustrates the difference between Intel® Stratix® 10 L-Tile/H-Tile ATX PLL and Intel® Arria® 10 ATX PLL.

Figure 7. Comparison between Interface Signals for Intel® Stratix® 10 L-Tile/H-Tile Transceiver ATX PLL and Intel® Arria® 10 Transceiver ATX PLL

Another change on Intel® Stratix® 10 L-Tile/H-Tile Transceiver PHY is the additional 1 bit added to the reconfig_address bus, compared to the Intel® Arria® 10 Transceiver PHY version. The same change is required for the Multi-rate PHY as it is created by using the Native PHY as the baseline.

The following figure illustrates how to connect the reconfig_address.

Figure 8. Block Diagram on Reconfiguration Address Connectivity for Intel® Stratix® 10 Ethernet Subsystem DesignThe example shown is based on the Ethernet design example model. For the blocks that are generated by Platform Designer, you can obtain the modules from the design example files.

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