GPIO IP User Guide: Arria® 10 and Cyclone® 10 GX Devices
ID
683136
Date
9/29/2025
Public
1.1. Release Information for GPIO IP
1.2. GPIO IP Features
1.3. GPIO IP Data Paths
1.4. GPIO IP Interface Signals
1.5. Verifying Resource Utilization and Design Performance
1.6. GPIO FPGA IP Parameter Settings
1.7. Register Packing
1.8. GPIO FPGA IP Timing
1.9. GPIO FPGA IP Design Examples
1.10. IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
1.11. GPIO IP User Guide Archives
1.12. Document Revision History for the GPIO IP User Guide: Arria® 10 and Cyclone® 10 GX Devices
1.9. GPIO FPGA IP Design Examples
The GPIO IP can generate design examples that match your IP configuration in the parameter editor. You can use these design examples as references for instantiating the IP and reviewing the expected behavior in simulations.
You can generate the design examples from the GPIO IP parameter editor. After you set the parameters that you want, click Generate Example Design. The IP parameter editor generates the design example source files in the directory you specify.
Figure 16. Source Files in the Generated Design Example Directory
Note: The .qsys files are for internal use during design example generation only. You cannot edit these .qsys files.