GPIO IP User Guide: Arria® 10 and Cyclone® 10 GX Devices

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ID 683136
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. GPIO IP User Guide: Arria® 10 and Cyclone® 10 GX Devices
1. GPIO IP User Guide: Arria® 10 and Cyclone® 10 GX Devices x
1.1. Release Information for GPIO IP 1.2. GPIO IP Features 1.3. GPIO IP Data Paths 1.4. GPIO IP Interface Signals 1.5. Verifying Resource Utilization and Design Performance 1.6. GPIO FPGA IP Parameter Settings 1.7. Register Packing 1.8. GPIO FPGA IP Timing 1.9. GPIO FPGA IP Design Examples 1.10. IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices 1.11. GPIO IP User Guide Archives 1.12. Document Revision History for the GPIO IP User Guide: Arria® 10 and Cyclone® 10 GX Devices
1.3. GPIO IP Data Paths x
1.3.1. Input Path 1.3.2. Output and Output Enable Paths
1.4. GPIO IP Interface Signals x
1.4.1. Shared Signals 1.4.2. Data Bit-Order for Data Interface 1.4.3. Input and Output Bus High and Low Bits 1.4.4. Data Interface Signals and Corresponding Clocks
1.8. GPIO FPGA IP Timing x
1.8.1. Timing Components 1.8.2. Delay Elements 1.8.3. Timing Analysis 1.8.4. Timing Closure Guidelines
1.8.3. Timing Analysis x
1.8.3.1. Single Data Rate Input Register 1.8.3.2. Full-Rate or Half-Rate DDIO Input Register 1.8.3.3. Single Data Rate Output Register 1.8.3.4. Full-Rate or Half-Rate DDIO Output Register
1.9. GPIO FPGA IP Design Examples x
1.9.1. GPIO FPGA IP Synthesizable Quartus® Prime Design Example Generating and Using the Design Example 1.9.2. GPIO FPGA IP Simulation Design Example
1.10. IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
1.10.1. Migrating Your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP Cores 1.10.2. Guideline: Swap datain_h and datain_l Ports in Migrated IP
1. GPIO IP User Guide: Arria® 10 and Cyclone® 10 GX Devices

1.9.1. GPIO FPGA IP Synthesizable Quartus® Prime Design Example

The synthesizable design example is a compilation-ready Platform Designer system that you can include in an Quartus® Prime project.

Generating and Using the Design Example

To generate the synthesizable Quartus® Prime design example from the source files, run the following command in the design example directory:

quartus_sh -t make_qii_design.tcl

To specify an exact device to use, run the following command:

quartus_sh -t make_qii_design.tcl [device_name]

The TCL script creates a qii directory that contains the ed_synth.qpf project file. You can open and compile this project in the Quartus® Prime software.

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