GPIO IP User Guide: Arria® 10 and Cyclone® 10 GX Devices
ID
683136
Date
9/29/2025
Public
1.1. Release Information for GPIO IP
1.2. GPIO IP Features
1.3. GPIO IP Data Paths
1.4. GPIO IP Interface Signals
1.5. Verifying Resource Utilization and Design Performance
1.6. GPIO FPGA IP Parameter Settings
1.7. Register Packing
1.8. GPIO FPGA IP Timing
1.9. GPIO FPGA IP Design Examples
1.10. IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
1.11. GPIO IP User Guide Archives
1.12. Document Revision History for the GPIO IP User Guide: Arria® 10 and Cyclone® 10 GX Devices
1.4.2. Data Bit-Order for Data Interface
Figure 9. Data Bit-Order ConventionThis figure shows the bit-order convention for the din, dout and oe data signals.
- If the data bus size value is SIZE, the LSB is at the right-most position.
- If the data bus size value is 2 × SIZE, the bus is made of two words of SIZE.
- If the data bus size value is 4 × SIZE, the bus is made of four words of SIZE.
- The LSB is in the right-most position of each word.
- The right-most word specifies the first word going out for output buses and the first word coming in for input buses.
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