GPIO IP User Guide: Arria® 10 and Cyclone® 10 GX Devices
ID
683136
Date
9/29/2025
Public
1.1. Release Information for GPIO IP
1.2. GPIO IP Features
1.3. GPIO IP Data Paths
1.4. GPIO IP Interface Signals
1.5. Verifying Resource Utilization and Design Performance
1.6. GPIO FPGA IP Parameter Settings
1.7. Register Packing
1.8. GPIO FPGA IP Timing
1.9. GPIO FPGA IP Design Examples
1.10. IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
1.11. GPIO IP User Guide Archives
1.12. Document Revision History for the GPIO IP User Guide: Arria® 10 and Cyclone® 10 GX Devices
1.3. GPIO IP Data Paths
Figure 1. High-Level View of Single-Ended GPIO
Data Path | Register Mode | |||
---|---|---|---|---|
Bypass | Simple Register | DDR I/O | ||
Full-Rate | Half-Rate | |||
Input | Data goes from the delay element to the core, bypassing all double data rate I/Os (DDIOs). | The full-rate DDIO operates as a simple register, bypassing half-rate DDIOs. The Fitter chooses whether to pack the register in the I/O or implement the register in the core, depending on the area and timing trade-offs. | The full-rate DDIO operates as a regular DDIO, bypassing the half-rate DDIOs. | The full-rate DDIO operates as a regular DDIO. The half-rate DDIOs convert full-rate data to half-rate data. |
Output | Data goes from the core straight to the delay element, bypassing all DDIOs. | The full-rate DDIO operates as a simple register, bypassing half-rate DDIOs. The Fitter chooses whether to pack the register in the I/O or implement the register in the core, depending on the area and timing trade-offs. | The full-rate DDIO operates as a regular DDIO, bypassing the half-rate DDIOs. | The full-rate DDIO operates as a regular DDIO. The half-rate DDIOs convert full-rate data to half-rate data. |
Bidirectional | The output buffer drives both an output pin and an input buffer. | The full-rate DDIO operates as a simple register. The output buffer drives both an output pin and an input buffer. | The full-rate DDIO operates as a regular DDIO. The output buffer drives both an output pin and an input buffer. The input buffer drives a set of three flip-flops. | The full-rate DDIO operates as a regular DDIO. The half-rate DDIOs convert full-rate data to half-rate. The output buffer drives both an output pin and an input buffer. The input buffer drives a set of three flip-flops. |
If you use asynchronous clear and preset signals, all DDIOs share these same signals.
Half-rate and full-rate DDIOs connect to separate clocks. When you use half-rate and full-rate DDIOs, the full-rate clock must run at twice the half-rate frequency. You can use different phase relationships to meet timing requirements.
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