GPIO IP User Guide: Arria® 10 and Cyclone® 10 GX Devices
ID
683136
Date
9/29/2025
Public
1.1. Release Information for GPIO IP
1.2. GPIO IP Features
1.3. GPIO IP Data Paths
1.4. GPIO IP Interface Signals
1.5. Verifying Resource Utilization and Design Performance
1.6. GPIO FPGA IP Parameter Settings
1.7. Register Packing
1.8. GPIO FPGA IP Timing
1.9. GPIO FPGA IP Design Examples
1.10. IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
1.11. GPIO IP User Guide Archives
1.12. Document Revision History for the GPIO IP User Guide: Arria® 10 and Cyclone® 10 GX Devices
1.8.4. Timing Closure Guidelines
For the GPIO input registers, the input I/O transfer is likely to fail the hold time if you do not set the input delay chain. This failure is caused by the clock delay being larger than the data delay.
To meet the hold time, add delay to the input data path using the input delay chain. In general, the input delay chain is around 60 ps per step at the –1 speed grade. To get an approximate input delay chain setting to pass the timing, divide the negative hold slack by 60 ps.
However, if the I/O PLL drives the clocks of the GPIO input registers (simple register or DDIO mode), you can set the compensation mode to source synchronous mode. The Fitter automatically configures the I/O PLL to improve the setup and hold slack for the input I/O timing analysis.
For the GPIO output and output enable registers, you can add delay to the output data and clock using the output and output enable delay chains.
- If you observe setup time violation, you can increase the output clock delay chain setting.
- If you observe hold time violation, you can increase the output data delay chain setting.