GPIO IP User Guide: Arria® 10 and Cyclone® 10 GX Devices
ID
683136
Date
9/29/2025
Public
1.1. Release Information for GPIO IP
1.2. GPIO IP Features
1.3. GPIO IP Data Paths
1.4. GPIO IP Interface Signals
1.5. Verifying Resource Utilization and Design Performance
1.6. GPIO FPGA IP Parameter Settings
1.7. Register Packing
1.8. GPIO FPGA IP Timing
1.9. GPIO FPGA IP Design Examples
1.10. IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
1.11. GPIO IP User Guide Archives
1.12. Document Revision History for the GPIO IP User Guide: Arria® 10 and Cyclone® 10 GX Devices
1.8.2. Delay Elements
The Quartus® Prime software does not automatically set delay elements to maximize slack in the I/O timing analysis. To close the timing or maximize slack, set the delay elements manually in the Quartus® Prime settings file (.qsf).
Delay Element | .qsf Assignment |
---|---|
Input Delay Element | set_instance_assignment –to <PIN> -name INPUT_DELAY_CHAIN <0..63> |
Output Delay Element | set_instance_assignment –to <PIN> -name OUTPUT_DELAY_CHAIN <0..15> |
Output Enable Delay Element | set_instance_assignment –to <PIN> -name OE_DELAY_CHAIN <0..15> |