GPIO IP User Guide: Arria® 10 and Cyclone® 10 GX Devices
ID
683136
Date
9/29/2025
Public
1.1. Release Information for GPIO IP
1.2. GPIO IP Features
1.3. GPIO IP Data Paths
1.4. GPIO IP Interface Signals
1.5. Verifying Resource Utilization and Design Performance
1.6. GPIO FPGA IP Parameter Settings
1.7. Register Packing
1.8. GPIO FPGA IP Timing
1.9. GPIO FPGA IP Design Examples
1.10. IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
1.11. GPIO IP User Guide Archives
1.12. Document Revision History for the GPIO IP User Guide: Arria® 10 and Cyclone® 10 GX Devices
1.9.2. GPIO FPGA IP Simulation Design Example
The simulation design example uses your GPIO IP parameter settings to build the IP instance connected to a simulation driver. The driver generates random traffic and internally checks the legality of the out going data.
Using the design example, you can run a simulation using a single command, depending on the simulator that you use. The simulation demonstrates how you can use the GPIO IP.
Generating and Using the Design Example
To generate the simulation design example from the source files for a Verilog simulator, run the following command in the design example directory:
quartus_sh -t make_sim_design.tcl
To generate the simulation design example from the source files for a VHDL simulator, run the following command in the design example directory:
quartus_sh -t make_sim_design.tcl VHDL
The TCL script creates a sim directory that contains subdirectories—one for each supported simulation tool. You can find the scripts for each simulation tool in the corresponding directories.