GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

ID 683136
Date 1/25/2022
Public
Document Table of Contents

Register Packing

The GPIO IP core allows you to pack register into the periphery to save area and resource utilization.

You can configure the full-rate DDIO on the input and output path as a flip flop. To do so, add the .qsf assignments listed in this table.

Table 12.  Register Packing QSF Assignments
Path QSF Assignment
Input register packing set_instance_assignment -name FAST_INPUT_REGISTER ON -to <path to register>
Output register packing set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to <path to register>
Output enable register packing set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to <path to register>
Note: These assignments do not guarantee register packing. However, these assignments enable the Fitter to find a legal placement. Otherwise, the Fitter keeps the flip flop in the core.

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