GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

ID 683136
Date 1/25/2022
Public
Document Table of Contents

Single Data Rate Output Register

Figure 15.  Single Data Rate Output Register


Table 16.  Single Data Rate Output Register .sdc Command Examples
Command Command Example Description
create_clock and create_generated_clock

create_clock -name sdr_out_clk -period "100 MHz" sdr_out_clk

create_generated_clock -source sdr_out_clk -name sdr_out_outclk sdr_out_outclk

Generate the source clock and the output clock to transmit.
set_output_delay set_output_delay -clock sdr_out_outclk 0.45 sdr_out_data Instructs the Timing Analyzer to analyze the output data to transmit against the output clock to transmit.

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