Visible to Intel only — GUID: sam1412835917323
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Release Information for GPIO Intel® FPGA IP
GPIO Intel® FPGA IP Features
GPIO Intel® FPGA IP Data Paths
GPIO Intel® FPGA IP Interface Signals
Verifying Resource Utilization and Design Performance
GPIO Intel® FPGA IP Parameter Settings
Register Packing
GPIO Intel® FPGA IP Timing
GPIO Intel® FPGA IP Design Examples
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
GPIO Intel® FPGA IP User Guide Archives
Document Revision History for GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Visible to Intel only — GUID: sam1412835917323
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Full-Rate or Half-Rate DDIO Output Register
The output side of the full-rate and half-rate DDIO output registers are the same.
Command | Command Example | Description |
---|---|---|
create_clock and create_generated_clock | create_clock -name ddio_out_fr_clk -period "200 MHz" ddio_out_fr_clk create_generated_clock -source ddio_out_fr_clk -name ddio_out_fr_outclk ddio_out_fr_outclk |
Generate the clocks to the DDIO and the clock to transmit. |
set_output_delay | set_output_delay -clock ddio_out_fr_outclk 0.55 ddio_out_fr_data set_output_delay -add_delay -clock_fall -clock ddio_out_fr_outclk 0.55 ddio_out_fr_data |
Instruct the Timing Analyzer to analyze the positive and negative data against the output clock. |
set_false_path | set_false_path -rise_from ddio_out_fr_clk -fall_to ddio_out_fr_outclk set_false_path -fall_from ddio_out_fr_clk -rise_to ddio_out_fr_outclk |
Instruct the Timing Analyzer to ignore the rising edge of the source clock against the falling edge of the output clock, and the falling edge of source clock against rising edge of output clock |