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1.1. Altera IP Catalog and Parameter Editor
1.2. Installing and Licensing Altera* IP Cores
1.3. Best Practices for Altera* IP
1.4. IP General Settings
1.5. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
1.6. Generating IP Cores ( Quartus® Prime Standard Edition)
1.7. Generating Example Designs for Altera* IP
1.8. Modifying an IP Variation
1.9. Upgrading IP Cores
1.10. Simulating Altera* IP Cores
1.11. Synthesizing IP Cores in Other EDA Tools
1.12. Support for the IEEE 1735 Encryption Standard
1.13. Introduction to Altera* IP Cores Revision History
1.14. Introduction to Altera* IP Cores Archives
1.10.4.1.1. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts
1.10.4.1.2. Sourcing Cadence Incisive* Simulator Setup Scripts
1.10.4.1.3. Sourcing Cadence Xcelium* Simulator Setup Scripts
1.10.4.1.4. Sourcing QuestaSim* Simulator Setup Scripts
1.10.4.1.5. Sourcing Synopsys VCS* (2-Step) Simulator Setup Scripts
1.10.4.1.6. Sourcing Synopsys VCS* (3-Step) Simulator Setup Scripts
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1.10.2. Supported Simulation Flows
The Quartus® Prime software supports scripted and specialized simulation flows.
Simulation Flow | Description |
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Scripted Simulation Flows | Scripted simulation supports custom control of all aspects of simulation, such as custom compilation commands, or multipass simulation flows. Use a version-independent top-level simulation script that sources Quartus® Prime-generated IP simulation setup scripts. The Quartus® Prime software can generate a combined simulator setup script for all IP cores, for each supported simulator. |
Run Simulation | You can use the Run Simulation feature in the Quartus® Prime Pro Edition software to integrate your supported third-party EDA simulator and automate generation of simulator-specific files and setup scripts, compilation of simulation libraries, and launch of your simulation. |
Qrun Flow | The Qrun flow optionally creates simulation files, including the functional simulation model, and any testbench (or example design) for the QuestaSim* and Questa* Intel® FPGA Edition FPGA Edition simulators only. The Qrun flow can automatically combine the compile, optimize, and simulate functions into a single step. |
Specialized Simulation Flows | Specialized simulation flows support various design scenarios:
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