Introduction to Altera® IP Cores

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ID 683102
Date 3/31/2025
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Introduction to Altera IP Cores
1. Introduction to Altera IP Cores x
1.1. Altera IP Catalog and Parameter Editor 1.2. Installing and Licensing Altera* IP Cores 1.3. Best Practices for Altera* IP 1.4. IP General Settings 1.5. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) 1.6. Generating IP Cores ( Quartus® Prime Standard Edition) 1.7. Generating Example Designs for Altera* IP 1.8. Modifying an IP Variation 1.9. Upgrading IP Cores 1.10. Simulating Altera* IP Cores 1.11. Synthesizing IP Cores in Other EDA Tools 1.12. Support for the IEEE 1735 Encryption Standard 1.13. Introduction to Altera* IP Cores Revision History 1.14. Introduction to Altera* IP Cores Archives
1.1. Altera IP Catalog and Parameter Editor x
1.1.1. The Parameter Editor
1.2. Installing and Licensing Altera* IP Cores x
1.2.1. Intel FPGA IP Evaluation Mode 1.2.2. Checking the IP License Status 1.2.3. FPGA IP Versioning 1.2.4. Adding IP to IP Catalog
1.5. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) x
1.5.1. IP Core Generation Output ( Quartus® Prime Pro Edition) 1.5.2. Scripting IP Core Generation
1.6. Generating IP Cores ( Quartus® Prime Standard Edition) x
1.6.1. IP Core Generation Output ( Quartus® Prime Standard Edition)
1.9. Upgrading IP Cores x
1.9.1. Upgrading IP Cores at Command-Line 1.9.2. Migrating IP Cores to a Different Device 1.9.3. Troubleshooting IP or Platform Designer System Upgrade
1.10. Simulating Altera* IP Cores x
1.10.1. Supported Simulators 1.10.2. Supported Simulation Flows 1.10.3. Generating IP Simulation Files 1.10.4. Scripting IP Simulation 1.10.5. Using NativeLink Simulation ( Quartus® Prime Standard Edition)
1.10.4. Scripting IP Simulation x
1.10.4.1. Generating a Combined Simulator Setup Script
1.10.4.1. Generating a Combined Simulator Setup Script x
1.10.4.1.1. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 1.10.4.1.2. Sourcing Cadence Incisive* Simulator Setup Scripts 1.10.4.1.3. Sourcing Cadence Xcelium* Simulator Setup Scripts 1.10.4.1.4. Sourcing QuestaSim* Simulator Setup Scripts 1.10.4.1.5. Sourcing Synopsys VCS* (2-Step) Simulator Setup Scripts 1.10.4.1.6. Sourcing Synopsys VCS* (3-Step) Simulator Setup Scripts
1.10.5. Using NativeLink Simulation ( Quartus® Prime Standard Edition) x
1.10.5.1. Setting Up NativeLink Simulation ( Quartus® Prime Standard Edition) 1.10.5.2. Generating IP Functional Simulation Models ( Quartus® Prime Standard Edition)
1.11. Synthesizing IP Cores in Other EDA Tools x
1.11.1. Instantiating IP Cores in HDL
1.11.1. Instantiating IP Cores in HDL x
1.11.1.1. Accessing HDL Code Templates
1.11.1.1. Accessing HDL Code Templates x
1.11.1.1.1. Example Top-Level Verilog HDL Module 1.11.1.1.2. Example Top-Level VHDL Module
1.12. Support for the IEEE 1735 Encryption Standard x
1.12.1. Introduction to the IEEE 1735 Standalone Encryptor 1.12.2. IEEE1735 Standalone Encryptor Modes
1.12.2. IEEE1735 Standalone Encryptor Modes x
1.12.2.1. Using Quartus Mode for IEEE1735 Encryption 1.12.2.2. Using Supported Simulator Mode for IEEE1735 Encryption 1.12.2.3. Using Partial Encryption
Answers to Top FAQs
1. Introduction to Altera IP Cores

1.12.2.2. Using Supported Simulator Mode for IEEE1735 Encryption

The IEEE1735 Standalone Encryptor can also encrypt a file to be read into simulators that the Quartus® Prime supports.
Refer to Supported Simulators for the current supported list.

In Supported Simulator Mode takes the Encryptor takes in one source file, and then generates one encrypted file. The --simulation option encrypts the files for all four supported simulators simultaneously. To encrypt for only one or more specific simulators, specify the simulator by specifying a value for the --simulation option. The valid options are aldec, cadence, mentor, synopsys.

  1. Use one of the following commands to use Supported Simulator Mode for encryption. Use a comma delimiter to specify multiple simulators. Do not enter spaces between the options. For example, --simulation=aldec,cadence.
    • Verilog HDL:
      encrypt_1735 --simulation --language=verilog <file_name>.v
    • VHDL:
      encrypt_1735 --simulation --language=vhdl <file_name>.vhd

    The Encryptor creates an encrypted file with the same file name, but with a new extension, such as some_file.vp and some_file.vhdp.

  2. To optionally change the name of the output file name, specify the -o option. For example:
    • Verilog: 
      encrypt_1735 --simulation --language=verilog -o=<new_file_name>.v \
   <file_name>.v
    • VHDL: 
      encrypt_1735 --simulation --language=vhdl -o=<new_file_name>.vhd \
   <file_name>.vhd
    The Encryptor generates an encrypted <new_file_name>.v file or <new_file_name>.vhd.
    Note: If you are encrypting files that are called by name in other parts of the source code, such as Verilog `include files, you must use the correct encrypted filename when you reference the files. Use the -o option to create the encrypted file with the original filename, so that the name does not include the default “p” in the extension (for example, <included_file_name>.v instead of <included_file_name>.vp).
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