Introduction to Altera® IP Cores

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ID 683102
Date 3/31/2025
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Introduction to Altera IP Cores
1. Introduction to Altera IP Cores x
1.1. Altera IP Catalog and Parameter Editor 1.2. Installing and Licensing Altera* IP Cores 1.3. Best Practices for Altera* IP 1.4. IP General Settings 1.5. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) 1.6. Generating IP Cores ( Quartus® Prime Standard Edition) 1.7. Generating Example Designs for Altera* IP 1.8. Modifying an IP Variation 1.9. Upgrading IP Cores 1.10. Simulating Altera* IP Cores 1.11. Synthesizing IP Cores in Other EDA Tools 1.12. Support for the IEEE 1735 Encryption Standard 1.13. Introduction to Altera* IP Cores Revision History 1.14. Introduction to Altera* IP Cores Archives
1.1. Altera IP Catalog and Parameter Editor x
1.1.1. The Parameter Editor
1.2. Installing and Licensing Altera* IP Cores x
1.2.1. Intel FPGA IP Evaluation Mode 1.2.2. Checking the IP License Status 1.2.3. FPGA IP Versioning 1.2.4. Adding IP to IP Catalog
1.5. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) x
1.5.1. IP Core Generation Output ( Quartus® Prime Pro Edition) 1.5.2. Scripting IP Core Generation
1.6. Generating IP Cores ( Quartus® Prime Standard Edition) x
1.6.1. IP Core Generation Output ( Quartus® Prime Standard Edition)
1.9. Upgrading IP Cores x
1.9.1. Upgrading IP Cores at Command-Line 1.9.2. Migrating IP Cores to a Different Device 1.9.3. Troubleshooting IP or Platform Designer System Upgrade
1.10. Simulating Altera* IP Cores x
1.10.1. Supported Simulators 1.10.2. Supported Simulation Flows 1.10.3. Generating IP Simulation Files 1.10.4. Scripting IP Simulation 1.10.5. Using NativeLink Simulation ( Quartus® Prime Standard Edition)
1.10.4. Scripting IP Simulation x
1.10.4.1. Generating a Combined Simulator Setup Script
1.10.4.1. Generating a Combined Simulator Setup Script x
1.10.4.1.1. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 1.10.4.1.2. Sourcing Cadence Incisive* Simulator Setup Scripts 1.10.4.1.3. Sourcing Cadence Xcelium* Simulator Setup Scripts 1.10.4.1.4. Sourcing QuestaSim* Simulator Setup Scripts 1.10.4.1.5. Sourcing Synopsys VCS* (2-Step) Simulator Setup Scripts 1.10.4.1.6. Sourcing Synopsys VCS* (3-Step) Simulator Setup Scripts
1.10.5. Using NativeLink Simulation ( Quartus® Prime Standard Edition) x
1.10.5.1. Setting Up NativeLink Simulation ( Quartus® Prime Standard Edition) 1.10.5.2. Generating IP Functional Simulation Models ( Quartus® Prime Standard Edition)
1.11. Synthesizing IP Cores in Other EDA Tools x
1.11.1. Instantiating IP Cores in HDL
1.11.1. Instantiating IP Cores in HDL x
1.11.1.1. Accessing HDL Code Templates
1.11.1.1. Accessing HDL Code Templates x
1.11.1.1.1. Example Top-Level Verilog HDL Module 1.11.1.1.2. Example Top-Level VHDL Module
1.12. Support for the IEEE 1735 Encryption Standard x
1.12.1. Introduction to the IEEE 1735 Standalone Encryptor 1.12.2. IEEE1735 Standalone Encryptor Modes
1.12.2. IEEE1735 Standalone Encryptor Modes x
1.12.2.1. Using Quartus Mode for IEEE1735 Encryption 1.12.2.2. Using Supported Simulator Mode for IEEE1735 Encryption 1.12.2.3. Using Partial Encryption
Answers to Top FAQs
1. Introduction to Altera IP Cores

1. Introduction to Altera IP Cores

Altera and strategic IP partners offer a broad portfolio of configurable IP cores optimized for Altera FPGA devices. The Quartus® Prime software installation includes the Altera* IP library. Integrate optimized and verified Altera* IP cores into your design to shorten design cycles and maximize performance. The Quartus® Prime software also supports integration of IP cores from other sources. Use the IP Catalog (Tools > IP Catalog) to efficiently parameterize and generate synthesis and simulation files for your custom IP variation.
Figure 1.  Altera* IP Catalog


The Altera* IP library includes the following types of IP cores:

Basic Functions Memory Interfaces and Controllers
Bridges and Adapters Processors and Peripherals
DSP University Program
Interface Protocols Verification

This document provides basic information about parameterizing, generating, upgrading, and simulating stand-alone IP cores in the Quartus® Prime software.


Section Content
Altera IP Catalog and Parameter Editor
Installing and Licensing Altera IP Cores
Best Practices for Altera IP
IP General Settings
Specifying the IP Parameters and Options ( Quartus Prime Pro Edition)
Generating IP Cores ( Quartus Prime Standard Edition)
Generating Example Designs for Altera IP
Modifying an IP Variation
Upgrading IP Cores
Simulating Altera IP Cores
Synthesizing IP Cores in Other EDA Tools
Support for the IEEE 1735 Encryption Standard
Introduction to Altera IP Cores Revision History
Introduction to Altera IP Cores Archives

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