Introduction to Altera® IP Cores

Download PDF
ID 683102
Date 3/31/2025
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Introduction to Altera IP Cores
1. Introduction to Altera IP Cores x
1.1. Altera IP Catalog and Parameter Editor 1.2. Installing and Licensing Altera* IP Cores 1.3. Best Practices for Altera* IP 1.4. IP General Settings 1.5. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) 1.6. Generating IP Cores ( Quartus® Prime Standard Edition) 1.7. Generating Example Designs for Altera* IP 1.8. Modifying an IP Variation 1.9. Upgrading IP Cores 1.10. Simulating Altera* IP Cores 1.11. Synthesizing IP Cores in Other EDA Tools 1.12. Support for the IEEE 1735 Encryption Standard 1.13. Introduction to Altera* IP Cores Revision History 1.14. Introduction to Altera* IP Cores Archives
1.1. Altera IP Catalog and Parameter Editor x
1.1.1. The Parameter Editor
1.2. Installing and Licensing Altera* IP Cores x
1.2.1. Intel FPGA IP Evaluation Mode 1.2.2. Checking the IP License Status 1.2.3. FPGA IP Versioning 1.2.4. Adding IP to IP Catalog
1.5. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) x
1.5.1. IP Core Generation Output ( Quartus® Prime Pro Edition) 1.5.2. Scripting IP Core Generation
1.6. Generating IP Cores ( Quartus® Prime Standard Edition) x
1.6.1. IP Core Generation Output ( Quartus® Prime Standard Edition)
1.9. Upgrading IP Cores x
1.9.1. Upgrading IP Cores at Command-Line 1.9.2. Migrating IP Cores to a Different Device 1.9.3. Troubleshooting IP or Platform Designer System Upgrade
1.10. Simulating Altera* IP Cores x
1.10.1. Supported Simulators 1.10.2. Supported Simulation Flows 1.10.3. Generating IP Simulation Files 1.10.4. Scripting IP Simulation 1.10.5. Using NativeLink Simulation ( Quartus® Prime Standard Edition)
1.10.4. Scripting IP Simulation x
1.10.4.1. Generating a Combined Simulator Setup Script
1.10.4.1. Generating a Combined Simulator Setup Script x
1.10.4.1.1. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 1.10.4.1.2. Sourcing Cadence Incisive* Simulator Setup Scripts 1.10.4.1.3. Sourcing Cadence Xcelium* Simulator Setup Scripts 1.10.4.1.4. Sourcing QuestaSim* Simulator Setup Scripts 1.10.4.1.5. Sourcing Synopsys VCS* (2-Step) Simulator Setup Scripts 1.10.4.1.6. Sourcing Synopsys VCS* (3-Step) Simulator Setup Scripts
1.10.5. Using NativeLink Simulation ( Quartus® Prime Standard Edition) x
1.10.5.1. Setting Up NativeLink Simulation ( Quartus® Prime Standard Edition) 1.10.5.2. Generating IP Functional Simulation Models ( Quartus® Prime Standard Edition)
1.11. Synthesizing IP Cores in Other EDA Tools x
1.11.1. Instantiating IP Cores in HDL
1.11.1. Instantiating IP Cores in HDL x
1.11.1.1. Accessing HDL Code Templates
1.11.1.1. Accessing HDL Code Templates x
1.11.1.1.1. Example Top-Level Verilog HDL Module 1.11.1.1.2. Example Top-Level VHDL Module
1.12. Support for the IEEE 1735 Encryption Standard x
1.12.1. Introduction to the IEEE 1735 Standalone Encryptor 1.12.2. IEEE1735 Standalone Encryptor Modes
1.12.2. IEEE1735 Standalone Encryptor Modes x
1.12.2.1. Using Quartus Mode for IEEE1735 Encryption 1.12.2.2. Using Supported Simulator Mode for IEEE1735 Encryption 1.12.2.3. Using Partial Encryption
Answers to Top FAQs
1. Introduction to Altera IP Cores

1.2.2. Checking the IP License Status

You can check the license status of all IP in an Quartus® Prime project by viewing the Assembler report.

To generate and view the Assembler report in the GUI:

  1. Click Assembler on the Compilation Dashboard.
  2. When the Assembler (and any prerequisite stages of compilation) complete, click the Report icon for the Assembler in the Compilation Dashboard.
    Assembler Report Icon in Compilation Dashboard
  3. Click the Encrypted IP Cores Summary report.
    Encrypted IP Cores Summary Report

To generate and view the Assembler report at the command line:

  1. Type the following command:
    quartus_asm <project name> -c  <project revision>
  2. View the output report in /output_files/<project_name>.asm.rpt. 
    +----------------------------------------------------------------------+
; Assembler Encrypted IP Cores Summary                                 ;
+--------+----------------------------------------------+--------------+
; Vendor ; IP Core Name                                 ; License Type ;
+--------+----------------------------------------------+--------------+
; Intel  ; PCIe SRIOV with 4-PFs and 2K-VFs (6AF7 00FB) ; Unlicensed   ;
; Intel  ; Signal Tap (6AF7 BCE1)                       ; Licensed     ;
; Intel  ; Signal Tap (6AF7 BCEC)                       ; Licensed     ;
+--------+----------------------------------------------+--------------+
Level Two Title