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1.1. Altera IP Catalog and Parameter Editor
1.2. Installing and Licensing Altera* IP Cores
1.3. Best Practices for Altera* IP
1.4. IP General Settings
1.5. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
1.6. Generating IP Cores ( Quartus® Prime Standard Edition)
1.7. Generating Example Designs for Altera* IP
1.8. Modifying an IP Variation
1.9. Upgrading IP Cores
1.10. Simulating Altera* IP Cores
1.11. Synthesizing IP Cores in Other EDA Tools
1.12. Support for the IEEE 1735 Encryption Standard
1.13. Introduction to Altera* IP Cores Revision History
1.14. Introduction to Altera* IP Cores Archives
1.10.4.1.1. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts
1.10.4.1.2. Sourcing Cadence Incisive* Simulator Setup Scripts
1.10.4.1.3. Sourcing Cadence Xcelium* Simulator Setup Scripts
1.10.4.1.4. Sourcing QuestaSim* Simulator Setup Scripts
1.10.4.1.5. Sourcing Synopsys VCS* (2-Step) Simulator Setup Scripts
1.10.4.1.6. Sourcing Synopsys VCS* (3-Step) Simulator Setup Scripts
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1.10.1. Supported Simulators
The Quartus® Prime software supports the following EDA simulator versions for RTL and gate-level simulation.
Vendor | Simulator | Version | Platform | Supports Siemens EDA Verification IP |
---|---|---|---|---|
Aldec | Active-HDL* | 15.0 | Windows* 64-bit | No |
Aldec | Riviera-PRO* | 2024.10 | Windows, Linux, 64-bit | No |
Cadence | Xcelium* Parallel Simulator | 23.09.004 | Linux 64-bit | Yes |
Altera | Questa*-Intel FPGA Edition | 2024.3 | Windows, Linux, 64-bit | Yes |
Siemens EDA | QuestaSim* Simulator2 | 2024.3 | Windows, Linux, 64-bit | Yes |
Synopsys | VCS | V-2023.12-SP2-1 | Linux 64-bit | Yes |
Note: Starting in version 25.1, the "VCS MX" tool flow is now referred to as the "VCS (3-step) flow" which is fully supported. The “VCS” tool flow is now referred to as “VCS (2-step) flow" which is also supported but is deprecated.
Related Information
2 QuestaSim* is the generic name for Questa Core and Questa Prime simulators.