Introduction to Altera® IP Cores

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ID 683102
Date 3/31/2025
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Introduction to Altera IP Cores
1. Introduction to Altera IP Cores x
1.1. Altera IP Catalog and Parameter Editor 1.2. Installing and Licensing Altera* IP Cores 1.3. Best Practices for Altera* IP 1.4. IP General Settings 1.5. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) 1.6. Generating IP Cores ( Quartus® Prime Standard Edition) 1.7. Generating Example Designs for Altera* IP 1.8. Modifying an IP Variation 1.9. Upgrading IP Cores 1.10. Simulating Altera* IP Cores 1.11. Synthesizing IP Cores in Other EDA Tools 1.12. Support for the IEEE 1735 Encryption Standard 1.13. Introduction to Altera* IP Cores Revision History 1.14. Introduction to Altera* IP Cores Archives
1.1. Altera IP Catalog and Parameter Editor x
1.1.1. The Parameter Editor
1.2. Installing and Licensing Altera* IP Cores x
1.2.1. Intel FPGA IP Evaluation Mode 1.2.2. Checking the IP License Status 1.2.3. FPGA IP Versioning 1.2.4. Adding IP to IP Catalog
1.5. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) x
1.5.1. IP Core Generation Output ( Quartus® Prime Pro Edition) 1.5.2. Scripting IP Core Generation
1.6. Generating IP Cores ( Quartus® Prime Standard Edition) x
1.6.1. IP Core Generation Output ( Quartus® Prime Standard Edition)
1.9. Upgrading IP Cores x
1.9.1. Upgrading IP Cores at Command-Line 1.9.2. Migrating IP Cores to a Different Device 1.9.3. Troubleshooting IP or Platform Designer System Upgrade
1.10. Simulating Altera* IP Cores x
1.10.1. Supported Simulators 1.10.2. Supported Simulation Flows 1.10.3. Generating IP Simulation Files 1.10.4. Scripting IP Simulation 1.10.5. Using NativeLink Simulation ( Quartus® Prime Standard Edition)
1.10.4. Scripting IP Simulation x
1.10.4.1. Generating a Combined Simulator Setup Script
1.10.4.1. Generating a Combined Simulator Setup Script x
1.10.4.1.1. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 1.10.4.1.2. Sourcing Cadence Incisive* Simulator Setup Scripts 1.10.4.1.3. Sourcing Cadence Xcelium* Simulator Setup Scripts 1.10.4.1.4. Sourcing QuestaSim* Simulator Setup Scripts 1.10.4.1.5. Sourcing Synopsys VCS* (2-Step) Simulator Setup Scripts 1.10.4.1.6. Sourcing Synopsys VCS* (3-Step) Simulator Setup Scripts
1.10.5. Using NativeLink Simulation ( Quartus® Prime Standard Edition) x
1.10.5.1. Setting Up NativeLink Simulation ( Quartus® Prime Standard Edition) 1.10.5.2. Generating IP Functional Simulation Models ( Quartus® Prime Standard Edition)
1.11. Synthesizing IP Cores in Other EDA Tools x
1.11.1. Instantiating IP Cores in HDL
1.11.1. Instantiating IP Cores in HDL x
1.11.1.1. Accessing HDL Code Templates
1.11.1.1. Accessing HDL Code Templates x
1.11.1.1.1. Example Top-Level Verilog HDL Module 1.11.1.1.2. Example Top-Level VHDL Module
1.12. Support for the IEEE 1735 Encryption Standard x
1.12.1. Introduction to the IEEE 1735 Standalone Encryptor 1.12.2. IEEE1735 Standalone Encryptor Modes
1.12.2. IEEE1735 Standalone Encryptor Modes x
1.12.2.1. Using Quartus Mode for IEEE1735 Encryption 1.12.2.2. Using Supported Simulator Mode for IEEE1735 Encryption 1.12.2.3. Using Partial Encryption
Answers to Top FAQs
1. Introduction to Altera IP Cores

1.13. Introduction to Altera* IP Cores Revision History

This document has the following revision history.
Document Version Quartus® Prime Version Changes
2025.03.31 25.1
  • Added Top FAQ navigation to cover page.
  • Updated text and screenshots throughout for Altera rebranding.
  • Updated Supported Simulators topic for latest supported versions.
  • Added new Generating Example Designs for Altera IP topic.
  • Updated the information in Upgrading IP Cores at Command-Line.
  • Updated Generating a Combined Simulator Setup Script for packaged subsystem IP limitation and workaround.
  • Added new Using the IEEE1735 Standalone Encryptor section.
2023.04.03 23.1
  • Updated Support for the IEEE 1735 Encryption Standard topic for new installed location of public encryption key.
  • Updated Quartus® Prime Pro Edition IP Version Upgrade Paths.
2021.09.27 21.3
  • Added support for Questa* Intel® FPGA Edition simulator.
  • Removed support for ModelSim - Intel FPGA Edition simulator.
  • Updated simulator support in Simulator Support for Mentor Verification IP Bus Functional Models (BFMs) topic.
  • Updated Quartus® Prime Pro Edition IP Version Upgrade Paths figure for latest versions.
  • Revised Generating IP Simulation Files topic for new simulation options.
2020.11.09 20.3
  • Revised "Introduction to Intel FPGA IP Cores" topic to include Bridges and Adapters and Intel FPGA Interconnect categories in IP Catalog. Updated IP Catalog image.
  • Revised wording of "Intel FPGA IP Versioning" topic for clarity.
  • Added screenshot to "Checking the IP License Status" topic.
  • Added "IP Version Upgrade Paths" diagram to "Upgrading IP Cores" topic.
  • Updated IP Port Differences Report image in "Troubleshooting IP or System Upgrade" topic.
2019.09.30 19.3
  • Added details to "Support for the IEEE 1735 Encryption Standard."
  • Added " Altera* IP Versioning" topic.
  • Added "Checking the IP License Status" topic.
2019.05.13 18.1 Updated heading title in "Support for the IEEE 1735 Encryption Standard."
2019.04.16 18.1
  • Added "Introduction to Altera* IP Cores Archives."
  • Updated the keyname and added --help information to "Support for the IEEE 1735 Encryption Standard."
2018.10.24 18.1
  • Updated information about obtaining IEEE 1735 Encryption key.
2018.09.24 18.1
  • Added statement that the Quartus® Prime software installer does not support spaces in the installation path.
  • Added "Intel FPGA IP Best Practices" topic.
2018.05.07 18.0
  • Updated screenshots of IP Catalog and Parameter Editor for latest IP names.
  • Added note about Generate Combined Simulator Setup Scripts command limitations.
  • Added information about generation of simulation files for Xcelium*
  • Revised product branding for Intel® standards.
  • Revised topics on Intel® FPGA IP Evaluation Mode (formerly OpenCore).
  • Added note that IP core encryption is supported only in Quartus® Prime Pro Edition.
  • Revised product branding for Intel® standards.

Date

Version

Changes

2016.10.31 16.1
  • Removed references to .qsys file creation during Quartus® Prime Pro Edition stand-alone IP generation.
  • Added references to .ip file creation during Quartus® Prime Pro Edition stand-alone IP generation.
  • Updated IP Core Generation Output files list and diagram.
  • Indicated distinctions between Quartus® Prime Pro Edition and Quartus® Prime Standard Edition features.
  • Added Support for IP Core Encryption topic.
2016.08.07 16.0
  • Intel rebranding.
2016.05.02 16.0
  • Described Generate Simulator Setup Script for IP feature.
  • Add information about unique hash codes preventing name collisions.
  • Removed support for NativeLink in Pro Edition.
  • Updated all GUI descriptions and screenshots for latest version.
2016.02.05 15.1.1
  • Corrected list of files ip-make-simscript generates.
  • Removed incorrect statement about running ip-make-simscript.
  • Revised Incorporating IP Simulation Scripts in Top-Level Scripts graphic.
2015.11.02 15.1.0
  • Added Generating Version-Agnostic IP Simulation Scripts topic.
  • Added example IP simulation script templates for supported simulators.
  • Added Incorporating IP Simulation Scripts in Top-Level Scripts topic.
  • Added Troubleshooting IP Upgrade topic.
  • Updated IP Catalog and parameter editor descriptions for GUI changes.
  • Updated IP upgrade and migration steps for latest GUI changes.
  • Updated Generating IP Cores process for GUI changes.
  • Updated Files Generated for IP Cores and Qsys system description.
  • Updated Quartus® Prime product name throughout.
2015.05.04 15.0
  • The latest version of the ModelSim-Altera software supports native, mixed language (VHDL/Verilog HDL/SystemVerilog) co-simulation of plain text HDL.
  • Added qsys_script IP core instantiation information.
  • Described changes to generating and processing of instance and entity names.
  • Added description of upgrading IP cores at the command line.
  • Updated procedures for upgrading and migrating IP cores.
  • Gate level timing simulation supported only for Cyclone IV and Stratix IV devices.
2014.12.1 14.1 Added information about new Assignments > Settings > IP Settings that control frequency of synthesis file regeneration and automatic addition of IP files to the project.

2014.08.18

14.0a10

  • Added information about specifying parameters for IP cores targeting Arria 10 devices.
  • Added information about the latest IP output for Quartus II version 14.0a10 targeting Arria 10 devices.
  • Added information about individual migration of IP cores to the latest devices.
  • Added information about editing existing IP variations.
Aug 2014 13.1
  • Changed title from Introduction to Megafunctions to Introduction to Altera IP Cores.
  • Increased scope of document to include updated information about licensing, customizing, upgrading, and simulating all Altera IP cores.
  • Replaced MegaWizard Plug-In Manager with IP Catalog information.

May 2014

14.0

  

May 2013

13.0

  • Reorganization of content into topics.
  • First tracking of changes in Document Revision History.
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