Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations

ID 683082
Date 6/20/2022

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Document Table of Contents Use Synchronous Clock Enables

To turn off a clock domain in a synchronous manner, use a synchronous clock enable signal. FPGAs efficiently support clock enable signals because there is a dedicated clock enable signal available on all device registers.

This scheme does not reduce power consumption as much as gating the clock at the source because the clock network keeps toggling, and performs the same function as a gated clock by disabling a set of registers. Insert a multiplexer in front of the data input of every register to either load new data, or copy the output of the register.

Figure 14. Synchronous Clock Enable

When designing for Intel® Stratix® 10 devices, consider that high fan-out clock enable signals can limit the performance achievable by the Hyper- Retimer. For specific recommendations, refer to the Intel® Stratix® 10 High-Performance Design Handbook.