Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations

ID 683082
Date 6/20/2022
Public

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1.4.3.2. Shift Register with Evenly Spaced Taps

The following examples show a Verilog HDL and VHDL 8-bit wide, 255-bit long shift register (W > 1 and M = 255) with evenly spaced taps at 64, 128, 192, and 254.

The synthesis software implements this function in a single ALTSHIFT_TAPS IP core and maps it to RAM in supported devices, which is allowed placement in dedicated RAM blocks or MLAB memory.

Verilog HDL 8-Bit Wide, 255-Bit Long Shift Register with Evenly Spaced Taps

module top (clk, shift, sr_in, sr_out, sr_tap_one, sr_tap_two,
				sr_tap_three );
	input clk, shift;
	input [7:0] sr_in;
	output [7:0] sr_tap_one, sr_tap_two, sr_tap_three, sr_out;
	reg [7:0] sr [254:0];
	integer n;
	always @ (posedge clk)
		begin
		if (shift == 1'b1)
			begin
			for (n = 254; n>0; n = n-1)
				begin
				sr[n] <= sr[n-1];
				end
			sr[0] <= sr_in;
		end
	end
	assign sr_tap_one = sr[64];
	assign sr_tap_two = sr[128];
	assign sr_tap_three = sr[192];
	assign sr_out = sr[254];
endmodule