Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations

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Date 6/20/2022
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Document Table of Contents
Document Table of Contents x
1. Recommended HDL Coding Styles 2. Recommended Design Practices 3. Managing Metastability with the Intel® Quartus® Prime Software 4. Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations Archive A. Intel® Quartus® Prime Pro Edition User Guides
1. Recommended HDL Coding Styles x
1.1. Using Provided HDL Templates 1.2. Instantiating IP Cores in HDL 1.3. Inferring Multipliers and DSP Functions 1.4. Inferring Memory Functions from HDL Code 1.5. Register and Latch Coding Guidelines 1.6. General Coding Guidelines 1.7. Designing with Low-Level Primitives 1.8. Recommended HDL Coding Styles Revision History
1.1. Using Provided HDL Templates x
1.1.1. Inserting HDL Code from a Provided Template
1.3. Inferring Multipliers and DSP Functions x
1.3.1. Inferring Multipliers 1.3.2. Inferring Multiply-Accumulator and Multiply-Adder Functions
1.4. Inferring Memory Functions from HDL Code x
1.4.1. Inferring RAM functions from HDL Code 1.4.2. Inferring ROM Functions from HDL Code 1.4.3. Inferring Shift Registers in HDL Code Shift Register Inference for Intel® Stratix® 10 and Intel® Agilex™ Devices Shift Register Inference for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 1.4.4. Inferring FIFOs in HDL Code
1.4.1. Inferring RAM functions from HDL Code x
1.4.1.1. Use Synchronous Memory Blocks 1.4.1.2. Avoid Unsupported Reset and Control Conditions 1.4.1.3. Check Read-During-Write Behavior 1.4.1.4. Controlling RAM Inference and Implementation 1.4.1.5. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 1.4.1.6. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 1.4.1.7. Simple Dual-Port, Dual-Clock Synchronous RAM 1.4.1.8. True Dual-Port Synchronous RAM 1.4.1.9. Mixed-Width Dual-Port RAM 1.4.1.10. RAM with Byte-Enable Signals 1.4.1.11. Specifying Initial Memory Contents at Power-Up
1.4.3. Inferring Shift Registers in HDL Code x
Shift Register Inference for Intel® Stratix® 10 and Intel® Agilex™ Devices Shift Register Inference for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 1.4.3.1. Simple Shift Register 1.4.3.2. Shift Register with Evenly Spaced Taps
1.4.4. Inferring FIFOs in HDL Code x
1.4.4.1. Dual Clock FIFO Example in Verilog HDL 1.4.4.2. Dual Clock FIFO Timing Constraints
1.5. Register and Latch Coding Guidelines x
1.5.1. Register Power-Up Values 1.5.2. Secondary Register Control Signals Such as Clear and Clock Enable 1.5.3. Latches
1.5.1. Register Power-Up Values x
1.5.1.1. Specifying a Power-Up Value
1.5.3. Latches x
1.5.3.1. Avoid Unintentional Latch Generation 1.5.3.2. Inferring Latches Correctly
1.6. General Coding Guidelines x
1.6.1. Tri-State Signals 1.6.2. Clock Multiplexing 1.6.3. Adder Trees 1.6.4. State Machine HDL Guidelines 1.6.5. Multiplexer HDL Guidelines 1.6.6. Cyclic Redundancy Check Functions 1.6.7. Comparator HDL Guidelines 1.6.8. Counter HDL Guidelines
1.6.3. Adder Trees x
1.6.3.1. Architectures with 6-Input LUTs in Adaptive Logic Modules
1.6.4. State Machine HDL Guidelines x
1.6.4.1. State Machine Power-Up 1.6.4.2. Verilog HDL State Machines 1.6.4.3. VHDL State Machines
1.6.4.2. Verilog HDL State Machines x
1.6.4.2.1. Verilog-2001 State Machine Coding Example 1.6.4.2.2. SystemVerilog State Machine Coding Example
1.6.4.3. VHDL State Machines x
1.6.4.3.1. VHDL State Machine Coding Example
1.6.5. Multiplexer HDL Guidelines x
1.6.5.1. Intel® Quartus® Prime Software Option for Multiplexer Restructuring 1.6.5.2. Multiplexer Types 1.6.5.3. Implicit Defaults in IF Statements 1.6.5.4. default or OTHERS CASE Assignment
1.6.5.2. Multiplexer Types x
1.6.5.2.1. Binary Multiplexers 1.6.5.2.2. Selector Multiplexers 1.6.5.2.3. Priority Multiplexers
1.6.6. Cyclic Redundancy Check Functions x
1.6.6.1. If Performance is Important, Optimize for Speed 1.6.6.2. Use Separate CRC Blocks Instead of Cascaded Stages 1.6.6.3. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 1.6.6.4. Take Advantage of Latency if Available 1.6.6.5. Save Power by Disabling CRC Blocks When Not in Use 1.6.6.6. Initialize the Device with the Synchronous Load (sload) Signal
2. Recommended Design Practices x
2.1. Following Synchronous FPGA Design Practices 2.2. HDL Design Guidelines 2.3. Use Clock and Register-Control Architectural Features 2.4. Implementing Embedded RAM 2.5. Design Assistant Design Rule Checking 2.6. Recommended Design Practices Revision History
2.1. Following Synchronous FPGA Design Practices x
2.1.1. Implementing Synchronous Designs 2.1.2. Asynchronous Design Hazards
2.2. HDL Design Guidelines x
2.2.1. Considerations for the Intel® Hyperflex™ FPGA Architecture 2.2.2. Optimizing Combinational Logic 2.2.3. Optimizing Clocking Schemes 2.2.4. Optimizing Physical Implementation and Timing Closure 2.2.5. Optimizing Power Consumption 2.2.6. Managing Design Metastability
2.2.2. Optimizing Combinational Logic x
2.2.2.1. Avoid Combinational Loops 2.2.2.2. Avoid Unintended Latch Inference 2.2.2.3. Avoid Delay Chains in Clock Paths 2.2.2.4. Use Synchronous Pulse Generators
2.2.3. Optimizing Clocking Schemes x
2.2.3.1. Register Combinational Logic Outputs 2.2.3.2. Avoid Asynchronous Clock Division 2.2.3.3. Avoid Ripple Counters 2.2.3.4. Use Multiplexed Clocks 2.2.3.5. Use Gated Clocks 2.2.3.6. Use Synchronous Clock Enables
2.2.3.5. Use Gated Clocks x
2.2.3.5.1. Recommended Clock-Gating Methods
2.2.4. Optimizing Physical Implementation and Timing Closure x
2.2.4.1. Planning Physical Implementation 2.2.4.2. Planning FPGA Resources 2.2.4.3. Optimizing for Timing Closure 2.2.4.4. Optimizing Critical Timing Paths
2.3. Use Clock and Register-Control Architectural Features x
2.3.1. Use Global Reset Resources 2.3.2. Use Global Clock Network Resources 2.3.3. Use Clock Region Assignments to Optimize Clock Constraints 2.3.4. Avoid Asynchronous Register Control Signals
2.3.1. Use Global Reset Resources x
2.3.1.1. Use Synchronous Resets 2.3.1.2. Using Asynchronous Resets 2.3.1.3. Use Synchronized Asynchronous Reset
2.3.3. Use Clock Region Assignments to Optimize Clock Constraints x
2.3.3.1. Clock Region Assignments in Intel® Stratix® 10 Devices 2.3.3.2. Clock Region Assignments in Intel® Arria® 10 and Older Device Families
2.5. Design Assistant Design Rule Checking x
2.5.1. Setting Up Design Assistant 2.5.2. Running Design Assistant During Compilation 2.5.3. Running Design Assistant in Analysis Mode 2.5.4. Cross-Probing from Design Assistant 2.5.5. Managing Design Assistant Rules 2.5.6. Design Assistant Rule Categories
2.5.1. Setting Up Design Assistant x
2.5.1.1. Design Assistant Rule Severity Levels
2.5.2. Running Design Assistant During Compilation x
2.5.2.1. Opening Design Assistant Rule Help
2.5.3. Running Design Assistant in Analysis Mode x
2.5.3.1. Launching Design Assistant from Chip Planner 2.5.3.2. Launching Design Assistant from Timing Analyzer
2.5.4. Cross-Probing from Design Assistant x
2.5.4.1. Cross-Probing from Design Assistant to Timing Analyzer 2.5.4.2. Cross-Probing from Design Assistant to Visualization Tools
2.5.5. Managing Design Assistant Rules x
2.5.5.1. Changing the Default Number of Violations per Rule 2.5.5.2. Enabling Rules for Specific Compiler Stages 2.5.5.3. Specifying Rule Parameters for a Specific Compiler Stage 2.5.5.4. Modifying Rule Severity Levels 2.5.5.5. Waiving Design Assistant Rules 2.5.5.6. Design Assistant Tags
2.5.5.5. Waiving Design Assistant Rules x
2.5.5.5.1. Creating Design Assistant Waivers 2.5.5.5.2. Design Assistant Waiver Dialog Box 2.5.5.5.3. Deleting Design Assistant Waivers 2.5.5.5.4. Design Assistant Waiver Tcl Commands 2.5.5.5.5. drc::add_waiver Command 2.5.5.5.6. drc::get_waivers Command 2.5.5.5.7. drc::report_waivers Command
3. Managing Metastability with the Intel® Quartus® Prime Software x
3.1. Metastability Analysis in the Intel® Quartus® Prime Software 3.2. Metastability and MTBF Reporting 3.3. MTBF Optimization 3.4. Reducing Metastability Effects 3.5. Scripting Support 3.6. Managing Metastability 3.7. Managing Metastability with the Intel® Quartus® Prime Software Revision History
3.1. Metastability Analysis in the Intel® Quartus® Prime Software x
3.1.1. Data Synchronization Register Chains 3.1.2. Identify Synchronizers for Metastability Analysis 3.1.3. How Timing Constraints Affect Synchronizer Identification and Metastability Analysis
3.2. Metastability and MTBF Reporting x
3.2.1. Metastability Reports 3.2.2. Synchronizer Data Toggle Rate in MTBF Calculation
3.2.1. Metastability Reports x
3.2.1.1. MTBF Summary Report 3.2.1.2. Synchronizer Summary Report 3.2.1.3. Synchronizer Chain Statistics Report in the Timing Analyzer
3.2.1.1. MTBF Summary Report x
3.2.1.1.1. Typical and Worst-Case MTBF of Design 3.2.1.1.2. Synchronizer Chains 3.2.1.1.3. Increasing Available Settling Time
3.3. MTBF Optimization x
3.3.1. Synchronization Register Chain Length
3.4. Reducing Metastability Effects x
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Increase the Number of Stages Used in Synchronizers 3.4.7. Select a Faster Speed Grade Device
3.5. Scripting Support x
3.5.1. Identifying Synchronizers for Metastability Analysis 3.5.2. Synchronizer Data Toggle Rate in MTBF Calculation 3.5.3. report_metastability and Tcl Command 3.5.4. MTBF Optimization 3.5.5. Synchronization Register Chain Length
1. Recommended HDL Coding Styles
2. Recommended Design Practices
3. Managing Metastability with the Intel® Quartus® Prime Software
4. Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations Archive
A. Intel® Quartus® Prime Pro Edition User Guides

1.4.3. Inferring Shift Registers in HDL Code

The Intel® Quartus® Prime software Analysis & Synthesis stage of the Compiler automatically detects and infers shift registers in your HDL code according to the following guidelines:

Shift Register Inference for Intel® Stratix® 10 and Intel® Agilex™ Devices

Because of the high prevalence of registers in routing segments of the Intel® Hyperflex™ architecture, the Compiler's threshold for shift register inference is increased for Intel® Stratix® 10 and Intel® Agilex™ devices. This increase in the threshold means that some logic that the Compiler infers as a shift register in a previous generation FPGA, may not be inferred as a shift register when targeting Intel® Stratix® 10 or Intel® Agilex™ devices. This threshold increase allows more register retiming, thus improving overall design performance.

The following criteria apply to shift register detection and inference for Intel® Stratix® 10 and Intel® Agilex™ devices.

Default shift register inference requirements for Intel® Stratix® 10 and Intel® Agilex™ Devices:

  1. The minimum number of registers inferred in the shift register is 64. When the width of a chain of registers is 1, the chain must contain at least 69 registers for synthesis to infer a shift register. From these 69 registers, synthesis does not include the first and second registers in the chain in the inferred shift register. Synthesis places these first and second shift registers in ALMs. Synthesis infers a 64 bit long shift register with the third through sixty sixth registers. Synthesis does not include the last three registers in the chain in the inferred shift register. Rather, synthesis places the last three registers in ALMs.
  2. The minimum depth of registers inferred in the shift register is 32. When the width of a chain of registers is two or more, the chain must contain at least 37 register levels for synthesis to infer a shift register. As in the first requirement, synthesis does not include the first and second registers levels in each chain in the inferred shift register, nor are the last three register levels.
Figure 2. Shift Register Inference for Intel® Stratix® 10 and Intel® Agilex™ Devices
  • With the following assignment, the total number of required registers (depth * width) drops to 37:
    set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
    Note: An additional stage of inference takes place during the early retiming stage as physical synthesis optimization recovers area for registers that have not been retimed.
  • With both of the following assignments, the total number of required registers (depth * width) drops to 13:
    set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
set_global_assignment -name PHYSICAL_SHIFT_REGISTER_INFERENCE=OFF
Note: Reducing the shift register inference threshold can negatively impact design performance, as the technique reduces the number of registers available for retiming.

Shift Register Inference for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

For Intel® Arria® 10 devices, Analysis & Synthesis detects a group of shift registers of the same length, and implements the registers using the Shift Register Intel® FPGA IP.

For automatic detection, all of the shift registers must have the following characteristics:

  • Use the same clock and clock enable
  • Have no other secondary signals
  • Have equally spaced taps that are at least three registers apart

Synthesis recognizes shift registers only for device families with dedicated RAM blocks. Intel® Quartus® Prime Pro Edition synthesis uses the following guidelines:

  • The Intel® Quartus® Prime software determines whether to infer the Shift Register Intel® FPGA IP based on the width of the registered bus (W), the length between each tap (L), or the number of taps (N).
  • If the Auto Shift Register Recognition option is set to Auto, Intel® Quartus® Prime Pro Edition synthesis determines which shift registers are implemented in RAM blocks for logic by using the following methods:
    • The Optimization Technique setting
    • Logic and RAM utilization information about the design
    • Timing information from Timing-Driven Synthesis
  • If the registered bus width is one ( W = 1 ), Intel® Quartus® Prime synthesis infers the shift register IP if the number of taps, times the length between each tap, is greater than or equal to 64 ( N x L > 64 ).
  • If the registered bus width is greater than one ( W > 1 ), and the registered bus width times the number of taps times the length between each tap is greater than or equal to 32 ( W × N × L > 32 ), then Intel® Quartus® Prime synthesis the Shift Register Intel® FPGA IP.
  • If the length between each tap (L) is not a power of two, Intel® Quartus® Prime synthesis needs external logic (LEs or ALMs) to decode the read and write counters, because of different sizes of shift registers. This extra decode logic eliminates the performance and utilization advantages of implementing shift registers in memory.

The registers that Intel® Quartus® Prime synthesis maps to the Shift Register Intel® FPGA IP, and places in RAM are not available in a Verilog HDL or VHDL output file for simulation tools, because their node names do not exist after synthesis.

Note: The Compiler cannot implement a shift register that uses a shift enable signal into MLAB memory; instead, the Compiler uses dedicated RAM blocks. To control the type of memory structure that implements the shift register, use the ramstyle attribute. For example: 
(* ramstyle = "mlab" *) my_shift_reg

Section Content
Simple Shift Register
Shift Register with Evenly Spaced Taps

Level Two Title