A newer version of this document is available. Customers should click here to go to the newest version.
1.1. Using Provided HDL Templates 1.2. Instantiating IP Cores in HDL 1.3. Inferring Multipliers and DSP Functions 1.4. Inferring Memory Functions from HDL Code 1.5. Register and Latch Coding Guidelines 1.6. General Coding Guidelines 1.7. Designing with Low-Level Primitives 1.8. Recommended HDL Coding Styles Revision History
220.127.116.11. Use Synchronous Memory Blocks 18.104.22.168. Avoid Unsupported Reset and Control Conditions 22.214.171.124. Check Read-During-Write Behavior 126.96.36.199. Controlling RAM Inference and Implementation 188.8.131.52. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 184.108.40.206. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 220.127.116.11. Simple Dual-Port, Dual-Clock Synchronous RAM 18.104.22.168. True Dual-Port Synchronous RAM 22.214.171.124. Mixed-Width Dual-Port RAM 126.96.36.199. RAM with Byte-Enable Signals 188.8.131.52. Specifying Initial Memory Contents at Power-Up
184.108.40.206. If Performance is Important, Optimize for Speed 220.127.116.11. Use Separate CRC Blocks Instead of Cascaded Stages 18.104.22.168. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 22.214.171.124. Take Advantage of Latency if Available 126.96.36.199. Save Power by Disabling CRC Blocks When Not in Use 188.8.131.52. Initialize the Device with the Synchronous Load (sload) Signal
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Increase the Number of Stages Used in Synchronizers 3.4.7. Select a Faster Speed Grade Device
2.3.3. Use Clock Region Assignments to Optimize Clock Constraints
The Intel® Quartus® Prime software determines how clock regions are assigned. You can override these assignments with Clock Region assignments to specify that a signal routed with global routing paths must use the specified clock region.
Clock Region assignments allow you to control the placement of the clock region for floorplanning reasons. For example, use a Clock Region assignment to ensure that a certain area of the device has access to a global signal, throughout your design iterations. A Clock Region assignment can also be used in cases of congestion involving global signal resources. By specifying a smaller clock region size, the assignment prevents a signal using spine clock resources in the excluded sectors that may be encountering clock-related congestion.
You can specify Clock Region assignments in the assignment editor.
Did you find the information on this page useful?