Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations

ID 683082
Date 6/20/2022
Public

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1.6.4.2.2. SystemVerilog State Machine Coding Example

Use the following coding style to describe state machines in SystemVerilog.

SystemVerilog State Machine Using Enumerated Types

The module enum_fsm is an example of a SystemVerilog state machine implementation that uses enumerated types.

In Intel® Quartus® Prime Pro Edition synthesis, the enumerated type that defines the states for the state machine must be of an unsigned integer type. If you do not specify the enumerated type as int unsigned, synthesis uses a signed int type by default. In this case, the Intel® Quartus® Prime software synthesizes the design, but does not infer or optimize the logic as a state machine.

module enum_fsm (input clk, reset, input int data[3:0], output int o);
enum int unsigned { S0 = 0, S1 = 2, S2 = 4, S3 = 8 } state, next_state;
always_comb begin : next_state_logic
	  next_state = S0;
	  case(state)
		S0: next_state = S1;
		S1: next_state = S2;
		S2: next_state = S3;
		S3: next_state = S3;
	  endcase
end
always_comb begin
	  case(state)
		 S0: o = data[3];
		 S1: o = data[2];
		 S2: o = data[1];
		 S3: o = data[0];
	  endcase
end
always_ff@(posedge clk or negedge reset) begin
	  if(~reset)
		 state <= S0;
	  else
		 state <= next_state;
end
endmodule