184.108.40.206. Optimizing Critical Timing Paths
Review the register placement and routing paths by clicking Tools > Chip Planner. Large timing failures on high fan-out control signals can be caused by any of the following conditions:
- Sub-optimal use of global networks
- Signals that traverse the chip on local routing without pipelining
- Failure to correct high fan-out by register duplication
For high-speed and high-bandwidth designs, optimize speed by reducing bus width and wire usage. To reduce wire usage, move the data as little as possible. For example, if a block of logic functions on a few bits of a word, store inactive bits in a FIFO or memory. Memory is cheaper and denser than registers, and reduces wire usage.