Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations

ID 683082
Date 10/04/2021
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1.4.3. Inferring Shift Registers in HDL Code

The Intel® Quartus® Prime software Analysis & Synthesis stage of the Compiler automatically detects and infers shift registers in your HDL code according to the following guidelines:

Shift Register Inference for Intel® Stratix® 10 and Intel® Agilex™ Devices

Because of the high prevalence of registers in routing segments of the Intel® Hyperflex™ architecture, the Compiler's threshold for shift register inference is increased for Intel® Stratix® 10 and Intel® Agilex™ devices. This increase in the threshold means that some logic that the Compiler infers as a shift register in a previous generation FPGA, may not be inferred as a shift register when targeting Intel® Stratix® 10 or Intel® Agilex™ devices. This threshold increase allows more register retiming, thus improving overall design performance.

The following criteria apply to shift register detection and inference for Intel® Stratix® 10 and Intel® Agilex™ devices.

Default shift register inference requirements for Intel® Stratix® 10 and Intel® Agilex™ Devices:

  1. The minimum number of registers inferred in the shift register is 64. When the width of a chain of registers is 1, the chain must contain at least 69 registers for synthesis to infer a shift register. From these 69 registers, synthesis does not include the first and second registers in the chain in the inferred shift register. Synthesis places these first and second shift registers in ALMs. Synthesis infers a 64 bit long shift register with the third through sixty sixth registers. Synthesis does not include the last three registers in the chain in the inferred shift register. Rather, synthesis places the last three registers in ALMs.
  2. The minimum depth of registers inferred in the shift register is 32. When the width of a chain of registers is two or more, the chain must contain at least 37 register levels for synthesis to infer a shift register. As in the first requirement, synthesis does not include the first and second registers levels in each chain in the inferred shift register, nor are the last three register levels.
Figure 2. Shift Register Inference for Intel® Stratix® 10 and Intel® Agilex™ Devices
  • With the following assignment, the total number of required registers (depth * width) drops to 37:
    set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
    Note: An additional stage of inference takes place during the early retiming stage as physical synthesis optimization recovers area for registers that have not been retimed.
  • With both of the following assignments, the total number of required registers (depth * width) drops to 13:
    set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
    set_global_assignment -name PHYSICAL_SHIFT_REGISTER_INFERENCE=OFF
Note: Reducing the shift register inference threshold can negatively impact design performance, as the technique reduces the number of registers available for retiming.

Shift Register Inference for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

For Intel® Arria® 10 devices, Analysis & Synthesis detects a group of shift registers of the same length, and implements the registers using the Shift Register Intel® FPGA IP.

For automatic detection, all of the shift registers must have the following characteristics:

  • Use the same clock and clock enable
  • Have no other secondary signals
  • Have equally spaced taps that are at least three registers apart

Synthesis recognizes shift registers only for device families with dedicated RAM blocks. Intel® Quartus® Prime Pro Edition synthesis uses the following guidelines:

  • The Intel® Quartus® Prime software determines whether to infer the Shift Register Intel® FPGA IP based on the width of the registered bus (W), the length between each tap (L), or the number of taps (N).
  • If the Auto Shift Register Recognition option is set to Auto, Intel® Quartus® Prime Pro Edition synthesis determines which shift registers are implemented in RAM blocks for logic by using the following methods:
    • The Optimization Technique setting
    • Logic and RAM utilization information about the design
    • Timing information from Timing-Driven Synthesis
  • If the registered bus width is one ( W = 1 ), Intel® Quartus® Prime synthesis infers the shift register IP if the number of taps, times the length between each tap, is greater than or equal to 64 ( N x L > 64 ).
  • If the registered bus width is greater than one ( W > 1 ), and the registered bus width times the number of taps times the length between each tap is greater than or equal to 32 ( W × N × L > 32 ), then Intel® Quartus® Prime synthesis the Shift Register Intel® FPGA IP.
  • If the length between each tap (L) is not a power of two, Intel® Quartus® Prime synthesis needs external logic (LEs or ALMs) to decode the read and write counters, because of different sizes of shift registers. This extra decode logic eliminates the performance and utilization advantages of implementing shift registers in memory.

The registers that Intel® Quartus® Prime synthesis maps to the Shift Register Intel® FPGA IP, and places in RAM are not available in a Verilog HDL or VHDL output file for simulation tools, because their node names do not exist after synthesis.

Note: The Compiler cannot implement a shift register that uses a shift enable signal into MLAB memory; instead, the Compiler uses dedicated RAM blocks. To control the type of memory structure that implements the shift register, use the ramstyle attribute. For example:
(* ramstyle = "mlab" *) my_shift_reg