Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations

ID 683082
Date 10/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

1.4.4.2. Dual Clock FIFO Timing Constraints

If you choose to code your own dual clock FIFO, you must also create appropriate timing constraints in Synopsis Design Constraints format (.sdc).

Typically, you set the read and write clock domains asynchronous to each other by using the set_clock_groups SDC command. You typically specify the set_clock_groups command in a top-level .sdc file.

Constrain the read and write pointer clock domain crossings with skew and net delay constraints.

A skew constraint ensures the gray-coded pointer values transfer correctly between the clock domains. A net delay constraint bounds the wire delay between the two clock domains, to help reduce latency through the FIFO.

In the RTL example above, the pointers cross clock domains at the ff_launch to ff_meta register path, in two instances of the synchronizer_ff_r2 entity.

The following example constraints are appropriate for the RTL above. You can customize the -from and -to names as necessary for your implementation.

# Skew from read to write domain
set_max_skew -from rd2wr|ff_launch[*] -to rd2wr|ff_meta[*] \
     -get_skew_value_from_clock_period 
src_clock_period -skew_value_multiplier 0.8
# Skew from write to read domain
set_max_skew -from wr2rd|ff_launch[*] -to wr2rd|ff_meta[*] \
     -get_skew_value_from_clock_period 
src_clock_period -skew_value_multiplier 0.8
# Net delay from read to write domain
set_net_delay -from rd2wr|ff_launch[*] -to rd2wr|ff_meta[*] \
     -get_value_from_clock_period 
dst_clock_period -value_multiplier 0.8 -max
# Net delay from write to read domain
set_net_delay -from wr2rd|ff_launch[*] -to wr2rd|ff_meta[*] \
     -get_value_from_clock_period
dst_clock_period -value_multiplier 0.8 -max

After writing the skew and net delay constraints in the .sdc file, specify an entity-bound .sdc file .qsf assignment to apply the constraints to the synchronizer register paths in all instances of your FIFO.

Use the name of the .sdc file containing these constraints in the entity-bound .sdc file assignment in your .qsf. Also provide the name of the FIFO entity to which the constraints apply.

The following .qsf assignment example assumes that you save the constraints in fifo_synchronizer.sdc in your project directory, and that the constraints therein apply to the dcfifo_example entity:

set_global_assignment -name SDC_ENTITY_FILE fifo_synchronizer.sdc \
     -entity dcfifo_example