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1.1. Using Provided HDL Templates 1.2. Instantiating IP Cores in HDL 1.3. Inferring Multipliers and DSP Functions 1.4. Inferring Memory Functions from HDL Code 1.5. Register and Latch Coding Guidelines 1.6. General Coding Guidelines 1.7. Designing with Low-Level Primitives 1.8. Recommended HDL Coding Styles Revision History
220.127.116.11. Use Synchronous Memory Blocks 18.104.22.168. Avoid Unsupported Reset and Control Conditions 22.214.171.124. Check Read-During-Write Behavior 126.96.36.199. Controlling RAM Inference and Implementation 188.8.131.52. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 184.108.40.206. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 220.127.116.11. Simple Dual-Port, Dual-Clock Synchronous RAM 18.104.22.168. True Dual-Port Synchronous RAM 22.214.171.124. Mixed-Width Dual-Port RAM 126.96.36.199. RAM with Byte-Enable Signals 188.8.131.52. Specifying Initial Memory Contents at Power-Up
184.108.40.206. If Performance is Important, Optimize for Speed 220.127.116.11. Use Separate CRC Blocks Instead of Cascaded Stages 18.104.22.168. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 22.214.171.124. Take Advantage of Latency if Available 126.96.36.199. Save Power by Disabling CRC Blocks When Not in Use 188.8.131.52. Initialize the Device with the Synchronous Load (sload) Signal
3.1. Metastability Analysis in the Intel® Quartus® Prime Software 3.2. Metastability and MTBF Reporting 3.3. MTBF Optimization 3.4. Reducing Metastability Effects 3.5. Scripting Support 3.6. Managing Metastability 3.7. Managing Metastability with the Intel® Quartus® Prime Software Revision History 3.8. Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations Archive
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Increase the Number of Stages Used in Synchronizers 3.4.7. Select a Faster Speed Grade Device
3.1.1. Synchronization Register Chains
A synchronization register chain, or synchronizer, is defined as a sequence of registers that meets the following requirements:
- The registers in the chain are all clocked by the same clock or phase-related clocks.
- The first register in the chain is driven asynchronously or from an unrelated clock domain.
- Each register fans out to only one register, except the last register in the chain.
The length of the synchronization register chain is the number of registers in the synchronizing clock domain that meet the above requirements. The figure shows a sample two-register synchronization chain.
Figure 45. Sample Synchronization Register Chain
The path between synchronization registers can contain combinational logic if all registers of the synchronization register chain are in the same clock domain. The figure shows an example of a synchronization register chain that includes logic between the registers.
Figure 46. Sample Synchronization Register Chain Containing Logic
The timing slack available in the register-to-register paths of the synchronizer allows a metastable signal to settle, and is referred to as the available settling time. The available settling time in the MTBF calculation for a synchronizer is the sum of the output timing slacks for each register in the chain. Adding available settling time with additional synchronization registers improves the metastability MTBF.
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