Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations

ID 683082
Date 10/04/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Cross-Probing from Design Assistant to Timing Analyzer

Some Design Assistant rule violations allow cross-probing into Timing Analyzer. For example, for a path that Design Assistant flags with a setup analysis violation due to delay added for hold, you can cross-probe into the Timing Analyzer to view more information on the affected path and edge.

Follow these steps to cross-probe from such Design Assistant rule violations to the Timing Analyzer:

  1. Compile the design through at least the Compiler's Plan stage.
  2. Locate a rule violation in the Design Assistant folder of the Compilation Report.
  3. Right-click the rule violation to display any Report Timing commands available for the violation.
    Figure 33. Cross Probing from Design Assistant Rule TMC-20210 Violations to Timing Analyzer
  4. Click the Report Timing command. The Timing Analyzer opens and reports the timing data for the violation path. Report Timing (Extra Info) includes Estimated Delay Added for Hold and Route Stage Congestion Impact extra data.