F-Tile Interlaken Intel® FPGA IP Design Example User Guide

ID 683069
Date 12/04/2023

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1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 23.4
IP Version 8.0.0

The F-Tile Interlaken Intel® FPGA IP core provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design.

The testbench and design example supports NRZ and PAM4 mode for F-tile devices. The F-Tile Interlaken Intel® FPGA IP core generates design examples for the following supported combinations of number of lanes and data rates.

Table 1.  IP Supported Combinations of Number of Lanes and Data RatesThe following combinations are supported in the Intel® Quartus® Prime Pro Edition software version 23.4
Number of Lanes Lane Rate (Gbps)
6.25 10.3125 12.5 25.78125 53.125 56.25 106.25
1 - - - - - - Yes
2 - - - - Yes - Yes
3 - - - - - - Yes
4 Yes - Yes Yes Yes - Yes
6 - - - Yes Yes - -
8 - Yes Yes Yes Yes - -
101 - - Yes Yes Yes Yes -
12 - Yes Yes Yes Yes Yes -
Note: For designs with 56.25 Gbps data rate, you may observe a minimum pulse width violation when using a device with a speed grade of -3.
Figure 1. Development Steps for the Design Example
The F-Tile Interlaken Intel® FPGA IP core design example supports the following features:
  • Internal TX to RX serial loopback mode
  • Automatically generates fixed size packets
  • Basic packet checking capabilities
  • Ability to use System Console to reset the design for re-testing purpose
Figure 2. High-level Block Diagram
1 For a 10-lane configuration design, the F-tile requires 12 lanes of TX PMA to enable bonded transceiver clocking for minimizing the channel skew.