F-Tile Interlaken Intel® FPGA IP Design Example User Guide

ID 683069
Date 12/04/2023
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1.2. Generating the Design

Figure 3. Procedure
Follow these steps to generate the design example and testbench:
  1. In the Intel® Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Intel® Quartus® Prime project, or click File > Open Project to open an existing Intel® Quartus® Prime project. The wizard prompts you to specify a device.
  2. Specify the device family Intel Agilex® 7 and select device with F-Tile for your design.
  3. In the IP Catalog, locate and double-click F-Tile Interlaken Intel FPGA IP. The New IP Variant window appears.
  4. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
  5. Click OK. The parameter editor appears.
    Figure 4. Example Design Tab
  6. On the IP tab, specify the parameters for your IP core variation.
  7. On the Example Design tab, select the Simulation option to generate the testbench. Select the Synthesis option to generate the hardware design example. You must select at least one of the Simulation and Synthesis options to generate the design example.
  8. For Generated HDL Format, both Verilog and VHDL option is available.
  9. For Target Development Kit, select the Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit.
    Note: When you select the Development Kit option, the pin assignments are set according to the Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit device part number and may differ from your selected device. If you intend to test the design on hardware on a different PCB, select the None option and make the appropriate pin assignments in the .qsf file
  10. Click Generate Example Design. The Select Example Design Directory window appears.
  11. If you want to modify the design example directory path or name from the defaults displayed (ilk_f_0_example_design), browse to the new path and type the new design example directory name.
  12. Click OK.
In the F-Tile Interlaken Intel FPGA IP design example, a SystemPLL is instantiated automatically, and connected to F-Tile Interlaken Intel FPGA IP core. The SystemPLL hierarchy path in the design example is:
The SystemPLL in the design example shares the same 156.26 MHz reference clock as the Transceiver.
Note: Very Short Reach (VSR) mode setting is added to the Design Example .qsf file to be used along with Intel Agilex® 7 I-Series Transceiver-SoC Development Kit. You must remove the VSR mode setting if it does not apply to your application.