1.5. Compiling and Configuring the Hardware Design Example
- Ensure the example design generation is complete.
- In the Intel® Quartus® Prime Pro Edition software, open the Intel® Quartus® Prime project <design_example_installation_dir>/example_design.qpf>.
- On the Processing menu, click Start Compilation.
- After successful compilation, a .sof file is available in your specified directory. Follow these steps to program the hardware example design on the Intel Agilex® 7 device with F-tile:
- Connect the Development Kit to the host computer.
- Launch the Clock Control application, which is part of the development kit. Set new frequencies for the design example as following:
- For NRZ mode:
- For PAM4 mode:
- Si5391-B (U45), OUT1: Set to the value of pll_ref_clk 2 to 156.25 MHz.
- Si5332 (U19), OUT1: Set to the value of mac_pll_ref_clk 2 to 156.25 MHz.
- Si5332 (U19), OUT6: Set to the value of mgmt_clk 2 to 100 MHz.
- For FHT or when EFIFO is enabled:
- Si5394 (U118), OUT3: Set to the value of systempll_ref_clk 2 per your design requirement.
- Click .
- Select a programming device. Add the Intel Agilex® 7 I-Series Transceiver-SoC Development Kit.
- Ensure that Mode is set to JTAG.
- Select the Intel Agilex® 7 I-Series device and click Add Device. The programmer displays a diagram of the connections between the devices on your board.
- Check the box for the .sof.
- Check the box in the Program/Configure column.
- Click Start.
2 The Clock Control GUI application cannot drive all the frequencies.