F-Tile Interlaken Intel® FPGA IP Design Example User Guide

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ID 683069
Date 12/04/2023
Public

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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling and Configuring the Hardware Design Example 1.6. Testing the Hardware Design Example
2. Design Example Description x
2.1. Design Example Components 2.2. Analog Parameters Settings 2.3. Design Example Flow 2.4. Interface Signals 2.5. Register Map 2.6. Reset
1. Quick Start Guide
2. Design Example Description
3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide

2.3. Design Example Flow

The F-Tile Interlaken Intel® FPGA IP hardware design example completes the following steps:
  1. Reset the the F-tile Interlaken Intel® FPGA IP and F-Tile.
  2. Release the reset on Interlaken IP (system reset) and F-tile TX (tile_tx_rst_n).
  3. Configures the F-tile Interlaken Intel® FPGA IP in the internal loopback mode.
  4. Release the reset of F-tile RX (tile_rx_rst_n).
  5. Sends a stream of Interlaken packets with predefined data in the payload to the TX user data transfer interface of the IP core.
  6. Checks the received packets and reports the status. The packet checker included in the hardware design example provides the following basic packet checking capabilities:
    • Check that the transmitted packet sequence is correct.
    • Checks that the received data matches the expected values by ensuring both the start of packet (SOP) and end of packet (EOP) counts align while data is being transmitted and received.
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