P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 683059
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express 2. IP Architecture and Functional Description 3. Advanced Features 4. Interfaces 5. Parameters 6. Testbench 7. Troubleshooting/Debugging 8. Intel® P-tile Avalon® Streaming IP for PCI Express* User Guide Archives 9. Document Revision History for the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide A. Configuration Space Registers B. Root Port Enumeration C. Implementation of Address Translation Services (ATS) in Endpoint Mode D. Packets Forwarded to the User Application in TLP Bypass Mode E. Using the Avery BFM for Intel P-Tile PCI Express Gen4 x16 Simulations F. Bifurcated Endpoint Support for Independent Warm Resets
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express x
1.1. Overview 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Performance and Resource Utilization 1.6. IP Core and Design Example Support Levels
1.1. Overview x
1.1.1. Standards and Specifications Compliance
2. IP Architecture and Functional Description x
2.1. Architecture 2.2. Functional Description
2.1. Architecture x
2.1.1. Clock Domains 2.1.2. Refclk 2.1.3. Reset
2.1.3. Reset x
2.1.3.1. Independent PERST
2.2. Functional Description x
2.2.1. PMA/PCS 2.2.2. Data Link Layer Overview 2.2.3. Transaction Layer Overview
3. Advanced Features x
3.1. PCIe* Port Bifurcation and PHY Channel Mapping 3.2. Virtualization Support 3.3. TLP Bypass Mode
3.2. Virtualization Support x
3.2.1. SR-IOV Support 3.2.2. VirtIO Support
3.2.1. SR-IOV Support x
3.2.1.1. SR-IOV Supported Features List 3.2.1.2. Implementation 3.2.1.3. VF to PF Mapping 3.2.1.4. Function Level Reset (FLR)
3.2.1.2. Implementation x
3.2.1.2.1. VF Error Flag Interface (for x16/x8 Cores Only)
3.2.2. VirtIO Support x
3.2.2.1. VirtIO Supported Features List 3.2.2.2. Overview 3.2.2.3. Parameters 3.2.2.4. VirtIO PCI Configuration Access Interface 3.2.2.5. Registers
3.2.2.5. Registers x
3.2.2.5.1. VirtIO Common Configuration Capability Register (Address: 0x012) 3.2.2.5.2. VirtIO Common Configuration BAR Indicator Register (Address: 0x013) 3.2.2.5.3. VirtIO Common Configuration BAR Offset Register (Address: 0x014) 3.2.2.5.4. VirtIO Common Configuration Structure Length Register (Address 0x015) 3.2.2.5.5. VirtIO Notifications Capability Register (Address: 0x016) 3.2.2.5.6. VirtIO Notifications BAR Indicator Register (Address: 0x017) 3.2.2.5.7. VirtIO Notifications BAR Offset Register (Address: 0x018) 3.2.2.5.8. VirtIO Notifications Structure Length Register (Address: 0x019) 3.2.2.5.9. VirtIO Notifications Notify Off Multiplier Register (Address: 0x01A) 3.2.2.5.10. VirtIO ISR Status Capability Register (Address: 0x02F) 3.2.2.5.11. VirtIO ISR Status BAR Indicator Register (Address: 0x030) 3.2.2.5.12. VirtIO ISR Status BAR Offset Register (Address: 0x031) 3.2.2.5.13. VirtIO ISR Status Structure Length Register (Address: 0x032) 3.2.2.5.14. VirtIO Device Specific Capability Register (Address: 0x033) 3.2.2.5.15. VirtIO Device Specific BAR Indicator Register (Address: 0x034) 3.2.2.5.16. VirtIO Device Specific BAR Offset Register (Address 0x035 ) 3.2.2.5.17. VirtIO Device Specific Structure Length Register (Address: 0x036) 3.2.2.5.18. VirtIO PCI Configuration Access Capability Register (Address: 0x037) 3.2.2.5.19. VirtIO PCI Configuration Access BAR Indicator Register (Address: 0x038) 3.2.2.5.20. VirtIO PCI Configuration Access BAR Offset Register (Address: 0x039) 3.2.2.5.21. VirtIO PCI Configuration Access Structure Length Register (Address: 0x03A) 3.2.2.5.22. VirtIO PCI Configuration Access Data Register (Address: 0x03B)
3.3. TLP Bypass Mode x
3.3.1. Overview 3.3.2. Register Settings for the TLP Bypass Mode 3.3.3. User Avalon® -MM Interface 3.3.4. Avalon® -ST Interface
3.3.2. Register Settings for the TLP Bypass Mode x
3.3.2.1. TLPBYPASS_ERR_EN (Address 0x104194) 3.3.2.2. TLPBYPASS_ERR_STATUS (Address 0x104190)
3.3.4. Avalon® -ST Interface x
3.3.4.1. Configuration TLP 3.3.4.2. Transmit Interface 3.3.4.3. Receive Interface 3.3.4.4. Malformed TLP 3.3.4.5. ECRC
4. Interfaces x
4.1. Overview 4.2. Clocks and Resets 4.3. Serial Data Interface 4.4. Avalon-ST Interface 4.5. Hard IP Status Interface 4.6. Interrupt Interface 4.7. Error Interface 4.8. Hot Plug Interface (RP Only) 4.9. Power Management Interface 4.10. Configuration Output Interface 4.11. Configuration Intercept Interface (EP Only) 4.12. Hard IP Reconfiguration Interface 4.13. PHY Reconfiguration Interface 4.14. Page Request Service (PRS) Interface (EP Only)
4.2. Clocks and Resets x
4.2.1. Interface Clock Signals 4.2.2. Resets
4.2.2. Resets x
4.2.2.1. Interface Reset Signals 4.2.2.2. Function-Level Reset (FLR) Interface (EP Only)
4.4. Avalon-ST Interface x
4.4.1. TLP Header and Data Alignment for the Avalon-ST RX and TX Interfaces 4.4.2. Avalon® -ST RX Interface 4.4.3. Avalon® -ST RX Interface rx_st_ready Behavior 4.4.4. RX Flow Control Interface 4.4.5. Avalon® -ST TX Interface 4.4.6. Avalon® -ST TX Interface tx_st_ready Behavior 4.4.7. TX Flow Control Interface 4.4.8. Tag Allocation
4.4.8. Tag Allocation x
4.4.8.1. Completion Buffer Size
4.6. Interrupt Interface x
4.6.1. Legacy Interrupts 4.6.2. MSI 4.6.3. MSI-X
4.6.3. MSI-X x
4.6.3.1. Implementing MSI-X Interrupts
4.7. Error Interface x
4.7.1. Completion Timeout Interface 4.7.2. VF Error Flags Interface
4.12. Hard IP Reconfiguration Interface x
4.12.1. Address Map for the User Avalon-MM Interface 4.12.2. Configuration Registers Access
4.12.1. Address Map for the User Avalon-MM Interface x
4.12.1.1. User Avalon-MM Control Register (Offset 0x104068)
4.12.2. Configuration Registers Access x
4.12.2.1. Using Direct User Avalon-MM Interface (Byte Access) 4.12.2.2. Using the Debug Register Interface Access (Dword Access)
5. Parameters x
5.1. Top-Level Settings 5.2. Core Parameters
5.2. Core Parameters x
5.2.1. Avalon® Parameters 5.2.2. Base Address Registers 5.2.3. PCI Express and PCI Capabilities Parameters 5.2.4. Device Identification Registers 5.2.5. Configuration, Debug and Extension Options
5.2.3. PCI Express and PCI Capabilities Parameters x
5.2.3.1. Device Capabilities 5.2.3.2. VirtIO Parameters 5.2.3.3. Link Capabilities 5.2.3.4. Legacy Interrupt Pin Register 5.2.3.5. MSI Capabilities 5.2.3.6. MSI-X Capabilities 5.2.3.7. Slot Capabilities 5.2.3.8. Latency Tolerance Reporting (LTR) 5.2.3.9. Process Address Space ID (PASID) 5.2.3.10. Device Serial Number Capability 5.2.3.11. Page Request Service (PRS) 5.2.3.12. Access Control Service (ACS) Capabilities 5.2.3.13. Power Management 5.2.3.14. Vendor Specific Extended Capability (VSEC) Registers 5.2.3.15. TLP Processing Hints (TPH) 5.2.3.16. Address Translation Services (ATS) Capabilities
5.2.3.1. Device Capabilities x
5.2.3.1.1. Multifunction and SR-IOV System Parameters
6. Testbench x
6.1. Endpoint Testbench 6.2. Test Driver Module 6.3. Root Port BFM
6.3. Root Port BFM x
6.3.1. BFM Memory Map 6.3.2. Configuration Space Bus and Device Numbering 6.3.3. Configuration of Root Port and Endpoint 6.3.4. Issuing Read and Write Transactions to the Application Layer 6.3.5. BFM Procedures and Functions
6.3.5. BFM Procedures and Functions x
6.3.5.1. ebfm_barwr Procedure 6.3.5.2. ebfm_barwr_imm Procedure 6.3.5.3. ebfm_barrd_wait Procedure 6.3.5.4. ebfm_barrd_nowt Procedure 6.3.5.5. ebfm_cfgwr_imm_wait Procedure 6.3.5.6. ebfm_cfgwr_imm_nowt Procedure 6.3.5.7. ebfm_cfgrd_wait Procedure 6.3.5.8. ebfm_cfgrd_nowt Procedure 6.3.5.9. BFM Configuration Procedures 6.3.5.10. BFM Shared Memory Access Procedures 6.3.5.11. BFM Log and Message Procedures 6.3.5.12. Verilog HDL Formatting Functions
6.3.5.9. BFM Configuration Procedures x
6.3.5.9.1. ebfm_cfg_rp_ep Procedure 6.3.5.9.2. ebfm_cfg_decode_bar Procedure
6.3.5.10. BFM Shared Memory Access Procedures x
6.3.5.10.1. Shared Memory Constants 6.3.5.10.2. shmem_write Task 6.3.5.10.3. shmem_read Function 6.3.5.10.4. shmem_display Verilog HDL Function 6.3.5.10.5. shmem_fill Procedure 6.3.5.10.6. shmem_chk_ok Function
6.3.5.11. BFM Log and Message Procedures x
6.3.5.11.1. ebfm_display Verilog HDL Function 6.3.5.11.2. ebfm_log_stop_sim Verilog HDL Function 6.3.5.11.3. ebfm_log_set_suppressed_msg_mask Task 6.3.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 6.3.5.11.5. ebfm_log_open Verilog HDL Function 6.3.5.11.6. ebfm_log_close Verilog HDL Function
6.3.5.12. Verilog HDL Formatting Functions x
6.3.5.12.1. himage1 6.3.5.12.2. himage2 6.3.5.12.3. himage4 6.3.5.12.4. himage8 6.3.5.12.5. himage16 6.3.5.12.6. dimage1 6.3.5.12.7. dimage2 6.3.5.12.8. dimage3 6.3.5.12.9. dimage4 6.3.5.12.10. dimage5 6.3.5.12.11. dimage6 6.3.5.12.12. dimage7
7. Troubleshooting/Debugging x
7.1. Hardware 7.2. Debug Toolkit
7.1. Hardware x
7.1.1. Debugging Link Training Issues 7.1.2. Debugging Data Transfer and Performance Issues
7.1.1. Debugging Link Training Issues x
7.1.1.1. Generic Tools and Utilities 7.1.1.2. Signal Tap II Logic Analyzer 7.1.1.3. Additional Debug Tools
7.1.2. Debugging Data Transfer and Performance Issues x
7.1.2.1. Advanced Error Reporting (AER) 7.1.2.2. Second-Level Debug Tools
7.2. Debug Toolkit x
7.2.1. Overview 7.2.2. Enabling the P-Tile Debug Toolkit 7.2.3. Launching the P-Tile Debug Toolkit 7.2.4. Using the P-Tile Debug Toolkit 7.2.5. Using the P-Tile Link Inspector
A. Configuration Space Registers x
A.1. Configuration Space Registers A.2. Configuration Space Registers for Virtualization A.3. Intel-Defined VSEC Capability Registers
A.1. Configuration Space Registers x
A.1.1. Register Access Definitions A.1.2. PCIe Configuration Header Registers A.1.3. PCI Express Capability Structures A.1.4. Physical Layer 16.0 GT/s Extended Capability Structure A.1.5. MSI-X Registers
A.2. Configuration Space Registers for Virtualization x
A.2.1. SR-IOV Virtualization Extended Capabilities Registers Address Map A.2.2. PCIe Configuration Registers for Each Virtual Function
A.2.2. PCIe Configuration Registers for Each Virtual Function x
A.2.2.1. Alternative Routing ID (ARI) Capability Structure A.2.2.2. TLP Processing Hint (TPH) Capability Structure A.2.2.3. Address Translation Services (ATS) Capability Structure A.2.2.4. Access Control Services (ACS) Capability Structure
A.2.2.1. Alternative Routing ID (ARI) Capability Structure x
A.2.2.1.1. ARI Enhanced Capability Header Register (Offset 0x0) A.2.2.1.2. ARI Capability and Control Register (Offset 0x4)
A.2.2.2. TLP Processing Hint (TPH) Capability Structure x
A.2.2.2.1. TPH Requester Enhanced Capability Header (Offset 0x0) A.2.2.2.2. TPH Requester Capability Register (Offset 0x4) A.2.2.2.3. TPH Requester Control Register (Offset 0x8)
A.2.2.3. Address Translation Services (ATS) Capability Structure x
A.2.2.3.1. ATS Enhanced Capability Header (Offset 0x0) A.2.2.3.2. ATS Capability Register and ATS Control Register (Offset 0x4)
A.2.2.4. Access Control Services (ACS) Capability Structure x
A.2.2.4.1. ACS Extended Capability Header (Offset 0x0) A.2.2.4.2. ACS Capability Register (Offset 0x4) A.2.2.4.3. ACS Control Register (Offset 0x6) A.2.2.4.4. Egress Control Vector (Offset 0x8)
A.3. Intel-Defined VSEC Capability Registers x
A.3.1. Intel-Defined VSEC Capability Header (Offset 00h) A.3.2. Intel-Defined Vendor Specific Header (Offset 04h) A.3.3. Intel Marker (Offset 08h) A.3.4. JTAG Silicon ID (Offset 0x0C - 0x18) A.3.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D) A.3.6. General Purpose Control and Status Register (Offset 0x30) A.3.7. Uncorrectable Internal Error Status Register (Offset 0x34) A.3.8. Uncorrectable Internal Error Mask Register (Offset 0x38) A.3.9. Correctable Internal Error Status Register (Offset 0x3C) A.3.10. Correctable Internal Error Mask Register (Offset 0x40)
C. Implementation of Address Translation Services (ATS) in Endpoint Mode x
C.1. Sending Translated/Untranslated Requests C.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) C.3. Invalidating Requests/Completions
D. Packets Forwarded to the User Application in TLP Bypass Mode x
D.1. EP TLP Bypass Mode (Upstream) D.2. RC TLP Bypass Mode (Downstream)
E. Using the Avery BFM for Intel P-Tile PCI Express Gen4 x16 Simulations x
E.1. Overview E.2. Generate the PCIe PIO Example Design E.3. Integrate Avery BFMs (Root Complex) E.4. Configure the Avery BFM and Update the Simulation Script E.5. Compile and Simulate E.6. View the Results
E.2. Generate the PCIe PIO Example Design x
E.2.1. Avalon® -ST PCIe PIO Example Design
F. Bifurcated Endpoint Support for Independent Warm Resets x
F.1. PCI Express Resets F.2. P-tile PCIe Design Constraints
F.2. P-tile PCIe Design Constraints x
F.2.1. P-tile Dual-Endpoint System Configurations
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express
2. IP Architecture and Functional Description
3. Advanced Features
4. Interfaces
5. Parameters
6. Testbench
7. Troubleshooting/Debugging
8. Intel® P-tile Avalon® Streaming IP for PCI Express* User Guide Archives
9. Document Revision History for the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide
A. Configuration Space Registers
B. Root Port Enumeration
C. Implementation of Address Translation Services (ATS) in Endpoint Mode
D. Packets Forwarded to the User Application in TLP Bypass Mode
E. Using the Avery BFM for Intel P-Tile PCI Express Gen4 x16 Simulations
F. Bifurcated Endpoint Support for Independent Warm Resets

7.2.4. Using the P-Tile Debug Toolkit

The following sections describe the different tabs and features available in the Debug Toolkit.

A. Main View

The main view tab lists a summary of the transmitter and receiver settings per channel for the given instance of the PCIe IP.

The following table shows the channel mapping when using bifurcated ports.
Table 117.  Channel Mapping for Bifurcated Ports
Toolkit Channel X16 Mode 2X8 Mode 4x4 Mode
Lane 0 Lane 0 Lane 0 Lane 0
Lane 1 Lane 1 Lane 1 Lane 1
Lane 2 Lane 2 Lane 2 Lane 2
Lane 3 Lane 3 Lane 3 Lane 3
Lane 4 Lane 4 Lane 4 Lane 0
Lane 5 Lane 5 Lane 5 Lane 1
Lane 6 Lane 6 Lane 6 Lane 2
Lane 7 Lane 7 Lane 7 Lane 3
Lane 8 Lane 8 Lane 0 Lane 0
Lane 9 Lane 9 Lane 1 Lane 1
Lane 10 Lane 10 Lane 2 Lane 2
Lane 11 Lane 11 Lane 3 Lane 3
Lane 12 Lane 12 Lane 4 Lane 0
Lane 13 Lane 13 Lane 5 Lane 1
Lane 14 Lane 14 Lane 6 Lane 2
Lane 15 Lane 15 Lane 7 Lane 3

B. Toolkit Parameters

The Toolkit parameters window has the following sub-tabs.

B.1. P-Tile Information

This lists a summary of the P-Tile PCIe IP parameter settings in the PCIe IP Parameter Editor when the IP was generated, as read by the P-Tile Debug Toolkit when initialized. If you have port bifurcation enabled in your design (for example, x8x8), then this tab will populate the P-tile information for each core (P0 core, P1 core, etc.).

All the information is read-only.

Use the Refresh button to read the settings.

Table 118.  P-Tile Available Parameter Settings
Parameter Values Descriptions
Intel Vendor ID 1172 Indicates the Vendor ID as set in the IP Parameter Editor.
Device ID 0 This is a unique identifier for the device that is assigned by the vendor.
Protocol PCIe Indicates the Protocol.
Port Type Root Port, Endpoint 5 Indicates the Hard IP Port type.
Intel IP Type intel_pcie_ptile_ast, intel_pcie_ptile_avmm Indicates the IP type used.
Advertised speed Gen3, Gen4 Indicates the advertised speed as configured in the IP Parameter Editor.
Advertised width x16, x8, x4 Indicates the advertised width as configured in the IP Parameter Editor.
Negotiated speed Gen3, Gen4 Indicates the negotiated speed during link training.
Negotiated width x16, x8, x4 Indicates the negotiated link width during link training.
Link status Link up, link down Indicates if the link (DL) is up or not.
LTSSM State Refer to Hard IP Status Interface. Indicates the current state of the link.
Lane Reversal True, False Indicates if lane reversal happens on the link.
Retimer 1 Detected, not detected Indicates if a retimer was detected between the Root Port and the Endpoint.
Retimer 2 Detected, not detected Indicates if a retimer was detected between the Root Port and the Endpoint.
Tx TLP Sequence Number Hexadecimal value Indicates the next transmit sequence number for the transmit TLP.
Tx Ack Sequence Timeout Hexadecimal value Indicates the ACK sequence number which is updated by receiving ACK/NAK DLLP.
Replay Timer Timeout Green, Red

Green: no timeout

Red: timeout
Malformed TLP Status Green, Red

Green: no malformed TLP

Red: malformed TLP detected
First Malformed TLP Error Pointer
  • AtomicOp address alignment
  • AtomicOp operand
  • AtomicOp byte enable
  • TLP length mismatch
  • Max payload size
  • Message TLP without TC0
  • Invalid TC
  • Unexpected route bit in Message TLP
  • Unexpected CRS status in Completion TLP
  • Byte enable
  • Memory address 4KB boundary
  • TLP prefix rules
  • Translation request rules
  • Invalid TLP type
  • Completion rules
  • Application
  
Figure 71. Example of P-Tile Parameter Settings

B.2. Event Counter

This tab allows you to read the error events like the number of receiver errors, framing errors, etc. for each port. You can use the Clear P0 counter/Clear P1 counter to reset the error counter.

Figure 72. Example of P-Tile Event Counter Tab

B.3. P0/P1 Configuration Space

This tab allows you to read the configuration space registers for that port. You will see a separate tab with the configuration space for each port.

Figure 73. Example of P-Tile PCIe Configuration Settings
Note: The per-lane information under the Configuration Space tab for each port corresponds to the logical lanes.

C. Channel Parameters

The channel parameters window allows you to read the transmitter and receiver settings for a given channel. It has the following 3 sub-windows. Use the Lane Refresh button to read the status of the General PHY, TX Path, and RX Path sub-windows for each channel.

Note: To refresh channel parameters for more than one lanes simultaneously, select the lanes under the Collection tab, right click and select Refresh.
Note: The per-lane information under the Channel Parameters tab corresponds to the physical lanes.

C.1. General PHY

This tab shows the reset status of the PHY.

Table 119.  General PHY Settings
  Parameters Values Descriptions
PHY Status PHY reset Normal, Reset

Indicates the PHY is in reset mode.

Normal: PHY is out of reset.

Reset: PHY is in reset.
Event Counter 6 to clear the counter values. Elastic buffer overflow Hex value Indicates elastic buffer overflow errors.
Elastic buffer underflow Hex value Indicates elastic buffer underflow errors.
Decode error Hex value Indicates decode errors.
Running disparity error Hex value Indicates running disparity errors.
SYNC header error Hex value Indicates SYNC header errors.
RX valid deassertion without EIEOS Hex value Indicates errors when RX valid deassertion occurs without EIEOS.

C.2. TX Path

This tab allows you to monitor the transmitter settings for the channel selected.

Table 120.  Transmitter Settings
  Parameters Values Descriptions
TX Status TX Reset Normal, Reset

Indicates if TX (TX datapath, TX settings) is in reset or normal operating mode.

Normal: TX is in normal operating mode.

Reset: TX is in reset.
TX Electrical Idle True, False

Indicates if TX is in electrical idle.

True: indicates TX is in electrical idle.

False: indicates TX is out of electrical idle.
TX PLL TX PLL lock Green, Red

Indicates if TX PLL is locked. This is dependent on the PLL selected as indicated by TX PLL select.

There is one set of PLLs per Quad. The TX path of each channel reads out the PLL status corresponding to that Quad.
  • TX path for Ch0 to 3: Status of PLLs in Quad0
  • TX path for Ch4 to 7: Status of PLLs in Quad1
  • TX path for Ch8 to 11: Status of PLLs in Quad2
  • TX path for Ch12 to 15: Status of PLLs in Quad3

Green: TX PLL is locked.

Red: TX PLL is not locked.
TX VOD Iboost level

Gen3: 15

Gen4: 15

Indicates the transmitter current boost level when the TX amplitude boost mode is enabled.

Vboost en

Gen3: Enable

Gen4: Enable

Indicates if the TX swing boost level is enabled.

Enable: TX swing boost is enabled.

Disable: TX swing boost is disabled.
Vboost level

Gen3: 5

Gen4: 5

 Indicates the TX Vboost level.
TX Equalization TX Equalization Status Not attempted, Completed, Unsuccessful Indicates transmitter equalization status. The TX local and remote parameters are valid only when the value of Equalization status is returned as completed, indicating equalization has completed successfully.
TX Local Preset P0 to P10 Indicates the P-tile transmitter driver preset value as requested by the link partner during the Equalization phase of link training. If the preset is not one of these values, then no value is shown.
Local Pre-shoot coefficient

Depends on the coefficient requested by the link partner.

Indicates P-tile transmitter driver output pre-emphasis (pre-cursor coefficient value).

Local main coefficient

Depends on the coefficient requested by the link partner.

Indicates P-tile transmitter driver output pre-emphasis (main cursor coefficient value).

Local post coefficient

Depends on the coefficient requested by the link partner.

Indicates P-tile transmitter driver output pre-emphasis (post-cursor coefficient value).

Remote Pre-shoot coefficient (†) Depends on the transmitter driver output of the link partner.

Indicates link partner's transmitter driver's output pre-cursor coefficient value, as received by P-tile during the Equalization phase of link training. When P-tile is configured in Endpoint mode, this value corresponds to the coefficient received during Phase 2 of Equalization.

Remote main coefficient (†) Depends on the transmitter driver output of the link partner.

Indicates link partner's transmitter driver's output main cursor coefficient value, as received by P-tile during the Equalization phase of link training. When P-tile is configured in Endpoint mode, this value corresponds to the coefficient received during Phase 2 of Equalization.

Remote post coefficient (†) Depends on the transmitter driver output of the link partner. Indicates the link partner's transmitter driver's output post-cursor coefficient value, as received by P-tile during the Equalization phase of link training. When P-tile is configured in Endpoint mode, this value corresponds to the coefficient received during Phase 2 of Equalization.
Remote full swing (fs) (†) Depends on the device capability of the link partner. Indicates the full swing value used by the link partner during the Equalization phase of link training.
Remote low frequency (lf) (†) Depends on the device capability of the link partner.

Indicates the low frequency value used by the link partner during the Equalization phase of link training.

Note: (†) Refer to the following sections of the PCI Express* Base Specification Revision 4.0: 4.2.3 Link Equalization Procedure for 8.0 GT/s and Higher Data Rates and 8.3.3 Tx Voltage Parameters.
Figure 74. Example of Transmitter Settings

C.3. RX Path

This tab allows you to monitor and control the receiver settings for the channel selected.

Table 121.  Receiver Settings
  Parameters Values Descriptions
RX Status RX Reset Normal, Reset

Indicates if RX (RX datapath, RX settings) is in reset or normal operating mode.

Normal: RX is in normal operating mode.

Reset: RX is in reset.
RX Polarity No polarity inversion, Polarity inversion

Indicates RX polarity inversion for the selected lane.

No polarity inversion: no polarity inversion on RX.

Polarity inversion: polarity inversion on RX.
RX Electrical Idle True, False

Indicates if RX is in electrical idle or not.

True: RX is in electrical idle.

False: RX is out of electrical idle.
Receiver Detected Green, Grey

Green: Far end receiver is detected.

Grey: Far end receiver is not detected.
RX CDR CDR Lock Green, Red

Indicates the CDR lock state.

Green: CDR is locked.

Red: CDR is not locked.
CDR Mode Locked to Reference (LTR), Locked to Data (LTD)

Indicates the CDR lock mode.

LTR: CDR is locked to reference clock.

LTD: CDR is locked to data.
RX Equalization RX ATT

Gen3: 0

Gen4: 0

Indicates the RX equalization attenuation level.
RX CTLE Boost

Gen3: 12

Gen4: 16

Indicates the RX CTLE boost value.
RX CTLE Pole

Gen3: 2

Gen4: 2

Indicates the RX CTLE pole value.
RX VGA1

Gen3: 5

Gen4: 5

Indicates the RX AFE first stage VGA gain value.
RX VGA2

Gen3: 5

Gen4: 5

Indicates the RX AFE second stage VGA gain value.
DFE Enable Enable, Disable

Indicates DFE adaptation is enabled for taps 1 - 5.

Enable: DFE adaptation is enabled for taps 1 - 5.

Disable: DFE adaptation is disabled for taps 1 - 5.
DFE Tap1 adapted value <-128 to 127>

Indicates the adapted value of DFE tap 1. This is a signed input (two's complement encoded).

DFE Tap2 adapted value <-32 to 31>

Indicates the adapted value of DFE tap 2. This is a signed input (two's complement encoded).

DFE Tap3 adapted value <-32 to 31>

Indicates the adapted value of DFE tap 3. This is a signed input (two's complement encoded).

DFE Tap4 adapted value <-32 to 31>

Indicates the adapted value of DFE tap 4. This is a signed input (two's complement encoded).

DFE Tap5 adapted value <-32 to 31>

Indicates the adapted value of DFE tap 5. This is a signed input (two's complement encoded).

Figure 75. Example of Receiver Settings

D. Eye Viewer

The P-Tile Debug Toolkit supports the Eye Viewer tool that allows you to plot the eye diagram for each channel. The Eye Viewer tool:
  • Provides a pictorial representation of the eye for each channel, both in the bifurcated (e.g., x8x8) and non-bifurcated (e.g., x16) configurations.

  • Provides information on the total eye height, total eye width and the eye margin from the sampling point to the left, right, top, and bottom of the eye for each lane.

    Intel recommends that the margin for each lane on your board be more than the mask in the horizontal and vertical directions to make sure that the channel is good and meets the PCIe specification.

  • Uses fixed step sizes in the horizontal and vertical directions.
  • Performs the eye margin at the following bit error rates (BER):
    • 8.0 GT/s (Gen3) @ e-8, 100% confidence level
    • 16.0 GT/s (Gen4) @ e-9, 90% confidence level
    • 8.0 GT/s (Gen3) and 16.0 GT/s (Gen4) @ e-12, 95% confidence level
Note: The P-Tile Avalon® Streaming Intel FPGA IP for PCI Express eye viewer feature of the Debug Toolkit does not support the independent error sampler for performing eye margining. The eye margining is performed on the actual data path. As a result, the eye margining may produce uncorrectable errors in the data stream and cause the LTSSM to go to the Recovery state. You may mask out all errors (ex. AER registers) while performing the eye margining and reset all error counters, error registers, etc. after margining completes.
  1. In the System Console Tools menu option, click on Eye View Tool.
    Note: The per-lane information under the Eye Viewer tab corresponds to the physical lanes.
    Figure 76. Opening the Eye Viewer
  2. This will open a new tab Eye View Tool next to the Main View tab. Choose the instance and channel for which you want to run the eye view tests.
    Figure 77. Opening the Instance and Channel
  3. Set the Eye Max BER. Two options are available: 1e-9 or 1e-12.
  4. Click Start to begin the eye measurement for the selected channel.
  5. The messages window displays information messages to indicate the eye view tool's progress.
    Figure 78. Eye View Tool Messages
  6. Once the eye plot is complete, the eye height, eye width and eye diagram are displayed.
    Figure 79. Sample Eye Plot for BER = 1e-9
    Figure 80. Sample Eye Plot for BER = 1e-12
    Note: Full eye plot is not drawn for BER = 1e-12.
5 The 22.2 and 22.1 versions of Intel® Quartus® Prime support enabling the Debug Toolkit for both Endpoint and Root Port modes, and for the Linux and Windows operating systems only. The 21.4 or earlier versions of Intel® Quartus® Prime only support the Debug Toolkit for the Endpoint mode.
6 Use Clear event counter
Level Two Title