P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 9/26/2022

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Document Table of Contents

A.3. Intel-Defined VSEC Capability Registers

Table 139.  Intel-Defined VSEC Capability Registers (0xD00 : 0xD58)
31 : 20 19 : 16 15 : 8 7 : 0 PCIe Byte Offset
Next Cap Offset Version PCI Express* Extended Capability ID 00h
VSEC Length VSEC Rev VSEC ID 04h
Intel Marker 08h
JTAG Silicon ID DW0 0Ch
JTAG Silicon ID DW1 10h
JTAG Silicon ID DW2 14h
JTAG Silicon ID DW3 18h
CvP Status User Configurable Device/Board ID 1Ch
CvP Mode Control 20h
CvP Data 2 24h
CvP Data 28h
CvP Programming Control 2Ch
General Purpose Control and Status 30h
Uncorrectable Internal Error Status Register 34h
Uncorrectable Internal Error Mask Register 38h
Correctable Error Status Register 3Ch
Correctable Error Mask Register 40h
SSM IRQ Request & Status 44h
SSM IRQ Result Code 1 Shadow 48h
SSM IRQ Result Code 2 Shadow 4Ch
SSM Mailbox 50h
SSM Credit 0 Shadow 54h
SSM Credit 1 Shadow 58h